[PATCH v2 1/1] Coldfire: add amcore board support
angelo <[email protected]>
| Newsgroups | gmane.linux.uclinux.devel |
|---|---|
| Message-ID | <[email protected]> |
This patch adds support for the amcore board, mcf5307 based. Patch adds also support for mcf5307. Signed-off-by: Angelo Dureghello<[email protected]> Cc: Jason Jin<[email protected]> --- Changes in v2: - Added missing entry to MAINTAINERS - Added missing entry to boards.cfg --- MAINTAINERS | 4 + arch/m68k/cpu/mcf530x/Makefile | 48 ++++ arch/m68k/cpu/mcf530x/config.mk | 30 +++ arch/m68k/cpu/mcf530x/cpu.c | 48 ++++ arch/m68k/cpu/mcf530x/cpu.h | 33 +++ arch/m68k/cpu/mcf530x/cpu_init.c | 160 +++++++++++++ arch/m68k/cpu/mcf530x/interrupts.c | 43 ++++ arch/m68k/cpu/mcf530x/speed.c | 38 +++ arch/m68k/cpu/mcf530x/start.S | 253 ++++++++++++++++++++ arch/m68k/include/asm/cache.h | 2 +- arch/m68k/include/asm/immap.h | 22 ++ arch/m68k/include/asm/immap_5307.h | 78 ++++++ arch/m68k/include/asm/m5307.h | 123 ++++++++++ board/sysam/amcore/Makefile | 43 ++++ board/sysam/amcore/amcore.c | 174 ++++++++++++++ board/sysam/amcore/config.mk | 23 ++ board/sysam/amcore/flash.c | 462 ++++++++++++++++++++++++++++++++++++ board/sysam/amcore/u-boot.lds | 101 ++++++++ boards.cfg | 1 + include/configs/amcore.h | 193 +++++++++++++++ include/flash.h | 1 + 21 files changed, 1879 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 2daee7d..5cb951f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1118,6 +1118,10 @@ Wolfgang Wegner<[email protected]> astro_mcf5373l MCF5373L +Angelo Dureghello<[email protected]> + + amcore mcf5307 + ######################################################################### # AVR32 Systems: # # # diff --git a/arch/m68k/cpu/mcf530x/Makefile b/arch/m68k/cpu/mcf530x/Makefile new file mode 100644 index 0000000..3c5a1c2 --- /dev/null +++ b/arch/m68k/cpu/mcf530x/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (c) 2011 Angelo Dureghello<[email protected]> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG + +LIB = $(obj)lib$(CPU).o + +START = start.o +COBJS = interrupts.o cpu.o speed.o cpu_init.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/m68k/cpu/mcf530x/config.mk b/arch/m68k/cpu/mcf530x/config.mk new file mode 100644 index 0000000..f7b01c6 --- /dev/null +++ b/arch/m68k/cpu/mcf530x/config.mk @@ -0,0 +1,30 @@ +# +# Copyright (c) 2011 Angelo Dureghello<[email protected]> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-d7 -msep-data + +cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') +is5307:=$(shell grep CONFIG_M5307 $(TOPDIR)/include/$(cfg)) + +ifneq (,$(findstring CONFIG_M5307,$(is5307))) +PLATFORM_CPPFLAGS += -mcpu=5307 +endif diff --git a/arch/m68k/cpu/mcf530x/cpu.c b/arch/m68k/cpu/mcf530x/cpu.c new file mode 100644 index 0000000..6f8ca3b --- /dev/null +++ b/arch/m68k/cpu/mcf530x/cpu.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2011 Angelo Dureghello<[email protected]> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include<common.h> +#include<command.h> +#include<asm/immap.h> + +#include "cpu.h" + +#ifdef CONFIG_M5307 +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + /* enable watchdog, set timeout to 0 and wait */ + mbar_writeByte(MCFSIM_SYPCR, 0xc0); + while (1); + + /* we don't return! */ + return 0; +} + +int checkcpu(void) +{ + char buf[32]; + + printf("CPU: Freescale Coldfire MCF5307 at %s MHz\n", + strmhz(buf, CONFIG_SYS_CLK)); + return 0; +} +#endif diff --git a/arch/m68k/cpu/mcf530x/cpu.h b/arch/m68k/cpu/mcf530x/cpu.h new file mode 100644 index 0000000..1accfcc --- /dev/null +++ b/arch/m68k/cpu/mcf530x/cpu.h @@ -0,0 +1,33 @@ +/* + * cpu.h + * + * Copyright (c) 2011 Angelo Dureghello<[email protected]> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CPU_H_ +#define _CPU_H_ + +#include<command.h> + +/* Use this to create board specific reset functions */ +void board_reset(void) __attribute__((__weak__)); + +#endif /* _CPU_H_ */ diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c new file mode 100644 index 0000000..f4a4ccb --- /dev/null +++ b/arch/m68k/cpu/mcf530x/cpu_init.c @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2011 Angelo Dureghello<[email protected]> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include<common.h> +#include<watchdog.h> +#include<asm/immap.h> + +#if defined(CONFIG_M5307) +/* + * Simple mcf5307 chip select module init. + * + * Note: this chip has an issue reported in the device "errata": + * MCF5307ER Rev 4.2 reports @ section 35: + * Corrupted Return PC in Exception Stack Frame + * When processing an autovectored interrupt an error can occur that + * causes 0xFFFFFFFF to be written as the return PC value in the + * exception stack frame. The problem is caused by a conflict between + * an internal autovector access and a chip select mapped to the IACK + * address space (0xFFFFXXXX). + * Workaround: + * Set the C/I bit in the chip select mask register (CSMR) for the + * chip select that is mapped to 0xFFFFXXXX. + * This will prevent the chip select from asserting for IACK accesses. + */ +#define MCF5307_SP_ERR_FIX(cs_base,mask) \ + if((cs_base+(mask&0xffff0000))>=0xffff0000)mask|=0x20 + +void init_csm(void) +{ + volatile csm_t *csm = (csm_t *) (MMAP_CSM); + +#if (defined(CONFIG_SYS_CS0_BASE)&& defined(CONFIG_SYS_CS0_MASK) \ +&& defined(CONFIG_SYS_CS0_CTRL)) + csm->csar0 = (CONFIG_SYS_CS0_BASE>>16); + csm->cscr0 = CONFIG_SYS_CS0_CTRL; + csm->csmr0 = CONFIG_SYS_CS0_MASK; + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE,csm->csmr0); +#else +#warning "Chip Select 0 are not initialized/used" +#endif +#if (defined(CONFIG_SYS_CS1_BASE)&& defined(CONFIG_SYS_CS1_MASK) \ +&& defined(CONFIG_SYS_CS1_CTRL)) + csm->csar1 = (CONFIG_SYS_CS1_BASE>>16); + csm->cscr1 = CONFIG_SYS_CS1_CTRL; + csm->csmr1 = CONFIG_SYS_CS1_MASK; + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE,csm->csmr1); +#endif +#if (defined(CONFIG_SYS_CS2_BASE)&& defined(CONFIG_SYS_CS2_MASK) \ +&& defined(CONFIG_SYS_CS2_CTRL)) + csm->csar2 = (CONFIG_SYS_CS2_BASE>>16); + csm->cscr2 = CONFIG_SYS_CS2_CTRL; + csm->csmr2 = CONFIG_SYS_CS2_MASK; + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE,csm->csmr2); +#endif +#if (defined(CONFIG_SYS_CS3_BASE)&& defined(CONFIG_SYS_CS3_MASK) \ +&& defined(CONFIG_SYS_CS3_CTRL)) + csm->csar3 =(CONFIG_SYS_CS3_BASE>>16); + csm->cscr3 = CONFIG_SYS_CS3_CTRL; + csm->csmr3 = CONFIG_SYS_CS3_MASK; + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE,csm->csmr3); +#endif +#if (defined(CONFIG_SYS_CS4_BASE)&& defined(CONFIG_SYS_CS4_MASK) \ +&& defined(CONFIG_SYS_CS4_CTRL)) + csm->csar4 = (CONFIG_SYS_CS4_BASE>>16); + csm->cscr4 = CONFIG_SYS_CS4_CTRL; + csm->csmr4 = CONFIG_SYS_CS4_MASK; + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS4_BASE,csm->csmr4); +#endif +#if (defined(CONFIG_SYS_CS5_BASE)&& defined(CONFIG_SYS_CS5_MASK) \ +&& defined(CONFIG_SYS_CS5_CTRL)) + csm->csar5 = (CONFIG_SYS_CS5_BASE>>16); + csm->cscr5 = CONFIG_SYS_CS5_CTRL; + csm->csmr5 = CONFIG_SYS_CS5_MASK; + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS5_BASE,csm->csmr5); +#endif +#if (defined(CONFIG_SYS_CS6_BASE)&& defined(CONFIG_SYS_CS6_MASK) \ +&& defined(CONFIG_SYS_CS6_CTRL)) + csm->csar6 = (CONFIG_SYS_CS6_BASE>>16); + csm->cscr6 = CONFIG_SYS_CS6_CTRL; + csm->csmr6 = CONFIG_SYS_CS6_MASK; + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS6_BASE,csm->csmr6); +#endif +#if (defined(CONFIG_SYS_CS7_BASE)&& defined(CONFIG_SYS_CS7_MASK) \ +&& defined(CONFIG_SYS_CS7_CTRL)) + csm->csar7 = (CONFIG_SYS_CS7_BASE>>16); + csm->cscr7 = CONFIG_SYS_CS7_CTRL; + csm->csmr7 = CONFIG_SYS_CS7_MASK; + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS7_BASE,csm->csmr7); +#endif +} + +/* + * Set up the memory map and initialize registers + */ +void cpu_init_f(void) +{ + mbar_writeByte(MCFSIM_MPARK, 0x00); + mbar_writeByte(MCFSIM_SYPCR, 0x00); + mbar_writeByte(MCFSIM_SWIVR, 0x0f); + mbar_writeByte(MCFSIM_SWSR, 0x00); + mbar_writeLong(MCFSIM_IMR, 0xfffffbff); + mbar_writeByte(MCFSIM_SWDICR, 0x00); + mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); + mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); + mbar_writeByte(MCFSIM_I2CICR, 0x00); + mbar_writeByte(MCFSIM_UART1ICR, 0x00); + mbar_writeByte(MCFSIM_UART2ICR, 0x00); + mbar_writeByte(MCFSIM_ICR6, 0x00); + mbar_writeByte(MCFSIM_ICR7, 0x00); + mbar_writeByte(MCFSIM_ICR8, 0x00); + mbar_writeByte(MCFSIM_ICR9, 0x00); + + /* Chipselect Init */ + init_csm(); + + /* enable instruction cache now */ + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(int port) +{ +} + +void arch_preboot_os(void) +{ + /* + * OS can change interrupt offsets and are about to boot the OS so + * we need to make sure we disable all async interrupts. + */ + mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); + mbar_writeByte(MCFSIM_TIMER2ICR, 0x00); +} +#endif diff --git a/arch/m68k/cpu/mcf530x/interrupts.c b/arch/m68k/cpu/mcf530x/interrupts.c new file mode 100644 index 0000000..17a438f --- /dev/null +++ b/arch/m68k/cpu/mcf530x/interrupts.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2011 Angelo Dureghello<[email protected]> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include<common.h> +#include<watchdog.h> +#include<asm/processor.h> +#include<asm/immap.h> + +#ifdef CONFIG_M5307 +int interrupt_init(void) +{ + enable_interrupts(); + + return 0; +} + +void dtimer_intr_setup(void) +{ + /* clearing TIMER2 mask, so enabling the related interrupt */ + mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR)& ~0x00000400); + /* set TIMER2 interrupt priority */ + mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI); +} +#endif diff --git a/arch/m68k/cpu/mcf530x/speed.c b/arch/m68k/cpu/mcf530x/speed.c new file mode 100644 index 0000000..42b55dd --- /dev/null +++ b/arch/m68k/cpu/mcf530x/speed.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2011 Angelo Dureghello<[email protected]> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include<common.h> +#include<asm/processor.h> +#include<asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ +int get_clocks (void) +{ +#if defined(CONFIG_M5307) + gd->cpu_clk = CONFIG_SYS_CLK; + gd->bus_clk = gd->cpu_clk / 2; +#endif + + return (0); +} diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S new file mode 100644 index 0000000..b00ec25 --- /dev/null +++ b/arch/m68k/cpu/mcf530x/start.S @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2011 Angelo Dureghello<[email protected]> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include<asm-offsets.h> +#include<config.h> +#include<timestamp.h> +#include "version.h" +#include<asm/cache.h> + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#define _START _start +#define _FAULT _fault + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; \ + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte + +/* If we come from a pre-loader we don't need an initial exception + * table. + */ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +.long 0x00000000 /* Flash offset is 0 until we setup CS0 */ +.long _START + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +#endif + + .text + .globl _start +_start: + nop + nop + move.w #0x2700,%sr + + move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set MBAR address + valid flag */ + move.c %d0, %MBAR + + move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0 + move.c %d0, %RAMBAR + + /* if we come from a pre-loader we have no exception table and + * therefore no VBR to set + */ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + move.l #CONFIG_SYS_FLASH_BASE, %d0 + movec %d0, %VBR +#endif + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + + /* set stackpointer to internal sram end - 80 (global data struct size + some bytes) + * get some stackspace for the first c-code, + */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CONFIG_SYS_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ +#if defined(DEBUG)&& (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)&& \ + defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP) + halt +#endif + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + + .globl _exc_handler +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" + .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index f9e2d15..e519dfa 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -31,7 +31,7 @@ #define CONFIG_CF_V2 #endif -#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x) +#if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x) #define CONFIG_CF_V3 #endif diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index 2aab463..515739f 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -256,6 +256,28 @@ #endif #endif /* CONFIG_M5282 */ +#ifdef CONFIG_M5307 +#include<asm/immap_5307.h> +#include<asm/m5307.h> + +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) + +#define CONFIG_SYS_INTR_BASE (MMAP_INTC) +#define CONFIG_SYS_NUM_IRQS (64) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) +#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) +#define CONFIG_SYS_TMRINTR_NO (31) +#define CONFIG_SYS_TMRINTR_MASK (0x00000400) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) +#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1)<< 8) +#endif +#endif /* CONFIG_M5307 */ + #if defined(CONFIG_MCF5301x) #include<asm/immap_5301x.h> #include<asm/m5301x.h> diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h new file mode 100644 index 0000000..f52a09c --- /dev/null +++ b/arch/m68k/include/asm/immap_5307.h @@ -0,0 +1,78 @@ +/* + * MCF5307 Internal Memory Map + * + * Copyright (c) 2011 Angelo Dureghello<[email protected]> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5307__ +#define __IMMAP_5307__ + +#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) +#define MMAP_CSM (CONFIG_SYS_MBAR + 0x00000080) +#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) + +typedef struct csm { + u16 csar0; /* Chip-select Address */ + u16 res0a; + u32 csmr0; /* Chip-select Mask */ + u16 res0b; + u16 cscr0; /* Chip-select Control */ + u16 csar1; + u16 res1a; + u32 csmr1; + u16 res1b; + u16 cscr1; + u16 csar2; + u16 res2a; + u32 csmr2; + u16 res2b; + u16 cscr2; + u16 csar3; + u16 res3a; + u32 csmr3; + u16 res3b; + u16 cscr3; + u16 csar4; + u16 res4a; + u32 csmr4; + u16 res4b; + u16 cscr4; + u16 csar5; + u16 res5a; + u32 csmr5; + u16 res5b; + u16 cscr5; + u16 csar6; + u16 res6a; + u32 csmr6; + u16 res6b; + u16 cscr6; + u16 csar7; + u16 res7a; + u32 csmr7; + u16 res7b; + u16 cscr7; +} csm_t; + +#endif /* __IMMAP_5307__ */ diff --git a/arch/m68k/include/asm/m5307.h b/arch/m68k/include/asm/m5307.h new file mode 100644 index 0000000..15007e9 --- /dev/null +++ b/arch/m68k/include/asm/m5307.h @@ -0,0 +1,123 @@ +/* + * mcf5307.h -- Definitions for Motorola Coldfire 5307 + * + * Copyright (c) 2011 Angelo Dureghello<[email protected]> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef mcf5307_h +#define mcf5307_h +/****************************************************************************/ + +/* + * useful definitions for reading/writing MBAR offset memory + */ +#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) +#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y +#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y +#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y + +/* + * Size of internal RAM + */ + +#define INT_RAM_SIZE 4096 /* RAMBAR - 4k */ + +/* + * Define the 5249 SIM register set addresses. + */ + +/***************** + ***** MBAR ***** + *****************/ +#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ +#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w) */ +#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ +#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ +#define MCFSIM_PAR 0x04 /* Parallel pin assignment register */ +#define MCFSIM_PLLCR 0x08 /* PLL Control register */ +#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */ + +#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */ +#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ +#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ +#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ +#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ +#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ +#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ +#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ +#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ +#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ +#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ +#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ +#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ + +#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ +#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ + +#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ +#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ +#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ + +#define MCFSIM_PADDR 0x244 /* Parallel data direction register */ +#define MCFSIM_PADAT 0x248 /* Parallel data direction register */ + +/* + * Some symbol defines for the above... + */ +#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ +#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ +#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ +#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */ +#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ +#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ +/* XXX - If needed, DMA ICRs go here */ + +/* + * Bit definitions for the ICR family of registers. + */ +#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ +#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ +#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ +#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ +#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ +#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ +#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ +#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ +#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ + +#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ +#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ +#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ +#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ + +/* + * Macros to read/set IMR register. It is 32 bits on the 5307. + */ + +#define mcf_getimr() \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) + +#define mcf_setimr(imr) \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); + +#endif /* mcf5307_h */ diff --git a/board/sysam/amcore/Makefile b/board/sysam/amcore/Makefile new file mode 100644 index 0000000..c585b19 --- /dev/null +++ b/board/sysam/amcore/Makefile @@ -0,0 +1,43 @@ +# +# Copyright (c) 2011 Angelo Dureghello<[email protected]> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS = $(BOARD).o flash.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c new file mode 100644 index 0000000..e65e7fc --- /dev/null +++ b/board/sysam/amcore/amcore.c @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2011 Angelo Dureghello<[email protected]> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include<common.h> +#include<command.h> +#include<malloc.h> +#include<asm/immap.h> + +/* + * board can have a K0108 lcd connected on the parallel port, + * wired as below: + * + * fc cpu P0 P1 P2 P3 P4 P5 P6 P7 P10 P11 P12 P13 P14 + * lcd D0 D1 D2 D3 D4 D5 D6 D7 CS1 CS2 RW DI E + * + * Starting up setting lines in high impedance + */ +int init_lcd (void) +{ + /* all pins set to parallel port except PP8 and PP9 */ + mbar_writeShort(MCFSIM_PAR, 0x300); + /* all outputs except P8 and P9 */ + mbar_writeShort(MCFSIM_PADDR, 0xfcff); + /* CSX and E all disabled, D(data), W(write) */ + mbar_writeShort(MCFSIM_PADAT, 0x0c00); +} + +int checkboard (void) +{ + puts ("Board: "); + puts ("AMCORE v.001(alpha)\n"); + + init_lcd(); + + return 0; +} + +/* aprox delay, to use before any timer init */ +void fudelay (int usec) +{ + int i=0; + + for (;i<10;++i) + { + __asm__ __volatile__ ("nop"); + } +} + +phys_size_t initdram (int board_type) +{ + icache_disable(); + + /* + SDRAM MT48LC4M32B2 details + + Memory block 0: 16 MB of SDRAM at address $00000000 + Port size: 32-bit port + + Memory block 0 wired as follows: + ColdFire Pin: A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 + SDRAM Pin: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10(CMD) A11 BA0 BA1 + + Ensure that there is a delay of at least 100 microseconds from processor + reset to the following code so that the SDRAM is ready for commands... + + write to DACR0 base address:0x0000, CASL:03, command bit 20, + CBM is OK to 3 ***, 32 bit port, continuos page mode, rest to 0 + */ + + fudelay(1000); + + /** + * DCR + * 0x26 mean Refresh period at 64msec (x4096 rows) + * 0x8000,0x8100,0x8200 are all valid, faster is 0x8000 (7G, tRC is>=70ns) + */ + mbar_writeShort(MCFSIM_DCR, 0x8226); + + /** + * DACR0 + * page mode on burst only (to be verified) 0x00 + * CMD on A20 0x0300 + */ + mbar_writeLong(MCFSIM_DACR0, 0x00003304); + mbar_writeLong(MCFSIM_DMR0, 0x00ff0001); + + // issue a PRECHARGE ALL + mbar_writeLong(MCFSIM_DACR0, 0x0000330c); + *((volatile unsigned long *)(0x00000004)) = 0xbeaddeed; + mbar_writeLong(MCFSIM_DACR0, 0x0000b304); + + fudelay(1000); + + *((volatile unsigned long *)(0x00000004)) = 0xbeaddeed; + mbar_writeLong(MCFSIM_DACR0, 0x0000b304); + + fudelay(1000); + + mbar_writeLong(MCFSIM_DACR0, 0x0000b344); + *((volatile unsigned long *)(0x00000c00)) = 0xbeaddeed; + + // Memory block 1 not in use (DMR1[V] = 0) + mbar_writeLong(MCFSIM_DMR1, 0x00040000); + mbar_writeLong(MCFSIM_DACR1, 0x00000000); + + icache_enable(); + + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +} + +int testdram (void) +{ + int i=0,x,rval=0; + + icache_disable(); + + const unsigned long a=0xaaaaaaaa; + const unsigned long b=0x55555555; + const unsigned long c=0xffffffff; + volatile unsigned long *p = (volatile unsigned long *)0; + volatile unsigned long *q; + + puts ("SRAM test:\n"); + + for (;i<16;++i) + { + printf ("testing MB %02d ...\n", i+1); + + q=p=(volatile unsigned long*)(1024*1024*i); + + for (x=0;x<65536;++x) { + *p++=0; + *p++=a; + *p++=b; + *p++=c; + } + for (x=0;x<65536;++x) { + if (*q++!=0) goto error; + if (*q++!=a) goto error; + if (*q++!=b) goto error; + if (*q++!=c) goto error; + } + } + puts ("test passed !\n"); + goto exit; + +error: + puts ("test failed !\n"); + rval=1; + +exit: + icache_enable(); + + return (rval); +} diff --git a/board/sysam/amcore/config.mk b/board/sysam/amcore/config.mk new file mode 100644 index 0000000..cb45c2c --- /dev/null +++ b/board/sysam/amcore/config.mk @@ -0,0 +1,23 @@ +# +# Copyright (c) 2011 Angelo Dureghello<[email protected]> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +CONFIG_SYS_TEXT_BASE = 0xffc00000 diff --git a/board/sysam/amcore/flash.c b/board/sysam/amcore/flash.c new file mode 100644 index 0000000..d2390f1 --- /dev/null +++ b/board/sysam/amcore/flash.c @@ -0,0 +1,462 @@ +/* + * Copyright (c) 2011 Angelo Dureghello<[email protected]> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include<common.h> + +#include<asm/immap.h> + +#ifndef CONFIG_SYS_FLASH_CFI +typedef unsigned short FLASH_PORT_WIDTH; +typedef volatile unsigned short FLASH_PORT_WIDTHV; + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define FLASH_CYCLE1 0x5555 +#define FLASH_CYCLE2 0x2aaa + +#define SYNC __asm__("nop") + +/*----------------------------------------------------------------------- + * Functions + */ + +ulong flash_get_size(FPWV * addr, flash_info_t * info); +int flash_get_offsets(ulong base, flash_info_t * info); +int write_word(flash_info_t * info, FPWV * dest, u16 data); +void inline spin_wheel(void); + +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; + +unsigned short swap (unsigned short value) +{ + return ((value<< 8) | (value>> 8)); +} + +ulong flash_init(void) +{ + ulong size = 0; + ulong fbase = 0; + + fbase = (ulong) CONFIG_SYS_FLASH_BASE; + flash_get_size((FPWV *) fbase,&flash_info[0]); + flash_get_offsets((ulong) fbase,&flash_info[0]); + fbase += flash_info[0].size; + size += flash_info[0].size; + + return size; +} + +int flash_get_offsets(ulong base, flash_info_t * info) +{ + int j, k; + + if ((info->flash_id& FLASH_VENDMASK) == FLASH_MAN_SST) { + + info->start[0] = base; + for (k = 0, j = 0; j< CONFIG_SYS_SST_SECT; j++, k++) { + info->start[k + 1] = info->start[k] + CONFIG_SYS_SST_SECTSZ; + info->protect[k] = 0; + } + } + + return ERR_OK; +} + +void flash_print_info(flash_info_t * info) +{ + int i; + + switch (info->flash_id& FLASH_VENDMASK) { + case FLASH_MAN_SST: + printf("SST "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id& FLASH_TYPEMASK) { + case FLASH_SST3201B: + printf("SST39VF3201B\n"); + break; + default: + printf("Unknown Chip Type\n"); + return; + } + + if (info->size> 0x100000) { + int remainder; + + printf(" Size: %ld", info->size>> 20); + + remainder = (info->size % 0x100000); + if (remainder) { + remainder>>= 10; + remainder = (int)((float) + (((float)remainder / (float)1024) * + 10000)); + printf(".%d ", remainder); + } + + printf("MB in %d Sectors\n", info->sector_count); + } else + printf(" Size: %ld KB in %d Sectors\n", + info->size>> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i< info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size(FPWV * addr, flash_info_t * info) +{ + u16 vend, flid; + + /* amcore board has bus bytes swapped */ + + addr[FLASH_CYCLE1] = (FPWV) 0xAA00AA00; /* for Atmel, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPWV) 0x55005500; /* for Atmel, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPWV) 0x90009000; /* selects Manufacture */ + + vend=swap(addr[0]); + + //printf ("vendor = %08X\n", vend); + + switch (vend) { + case (u8) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + flid = swap(addr[1]); + break; + default: + printf("Unknown Flash\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + + *addr = (FPW) 0xF000F000; + return (0); /* no or unknown flash */ + } + + //printf ("flash id = %08X\n", flid); + + switch (flid) { + case (u16) SST_ID_xF3201B: + info->flash_id += FLASH_SST3201B; + break; + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + info->sector_count = 0; + info->size = 0; + info->sector_count = CONFIG_SYS_SST_SECT; + info->size = CONFIG_SYS_SST_SECT * CONFIG_SYS_SST_SECTSZ; + + /* reset ID mode */ + *addr = (FPWV) 0xF000F000; + + if (info->sector_count> CONFIG_SYS_MAX_FLASH_SECT) { + printf("** ERROR: sector count %d> max (%d) **\n", + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; + } + + return (info->size); +} + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + FPWV *addr; + int flag, prot, sect, count; + ulong type, start, last; + int rcode = 0, flashtype = 0; + + if ((s_first< 0) || (s_first> s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; + } + + type = (info->flash_id& FLASH_VENDMASK); + + switch (type) { + case FLASH_MAN_SST: + flashtype = 1; + break; + default: + type = (info->flash_id& FLASH_VENDMASK); + printf("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect<= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + else + printf("\n"); + + flag = disable_interrupts(); + + start = get_timer(0); + last = start; + + if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) { + if (prot == 0) { + addr = (FPWV *) info->start[0]; + + addr[FLASH_CYCLE1] = 0xAA00; /* unlock */ + addr[FLASH_CYCLE2] = 0x5500; /* unlock */ + addr[FLASH_CYCLE1] = 0x8000; /* erase mode */ + addr[FLASH_CYCLE1] = 0xAA00; /* unlock */ + addr[FLASH_CYCLE2] = 0x5500; /* unlock */ + *addr = 0x3000; /* erase chip */ + + count = 0; + start = get_timer(0); + + while ((*addr& 0x8000) != 0x8000) { + if (count++> 0x10000) { + spin_wheel(); + count = 0; + } + + if (get_timer(start)> CONFIG_SYS_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *addr = 0xF000; /* reset to read mode */ + + return 1; + } + } + + *addr = 0xF000; /* reset to read mode */ + + printf("\b. done\n"); + + if (flag) + enable_interrupts(); + + return 0; + } else if (prot == CONFIG_SYS_SST_SECT) { + return 1; + } + } + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + + addr = (FPWV *) (info->start[sect]); + + printf("."); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + switch (flashtype) { + case 1: + { + FPWV *base; /* first address in bank */ + + flag = disable_interrupts(); + + base = (FPWV *) (CONFIG_SYS_FLASH_BASE); /* First sector */ + + base[FLASH_CYCLE1] = 0xAA00; /* unlock */ + base[FLASH_CYCLE2] = 0x5500; /* unlock */ + base[FLASH_CYCLE1] = 0x8000; /* erase mode */ + base[FLASH_CYCLE1] = 0xAA00; /* unlock */ + base[FLASH_CYCLE2] = 0x5500; /* unlock */ + *addr = 0x5000; /* erase sector */ + + if (flag) + enable_interrupts(); + + while ((*addr& 0x8000) != 0x8000) { + if (get_timer(start)> + CONFIG_SYS_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *addr = 0xF000; /* reset to read mode */ + + rcode = 1; + break; + } + } + + *addr = 0xF000; /* reset to read mode */ + break; + } + } /* switch (flashtype) */ + } + } + printf(" done\n"); + + if (flag) + enable_interrupts(); + + return rcode; +} + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp, count; + u16 data; + int rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) + return 4; + + /* get lower word aligned address */ + wp = addr; + port_width = sizeof(FPW); + + /* handle unaligned start bytes */ + if (wp& 1) { + data = *((FPWV *) wp); + data = (data<< 8) | *src; + + if ((rc = write_word(info, (FPWV *) wp, data)) != 0) + return (rc); + + wp++; + cnt -= 1; + src++; + } + + while (cnt>= 2) { + /* + * writing words here + */ + count = 0; + data = *((FPWV *) src); + + if ((rc = write_word(info, (FPWV *) wp, data)) != 0) + return (rc); + + wp += 2; + src += 2; + cnt -= 2; + + if (count++> 0x800) { + spin_wheel(); + count = 0; + } + } + /* handle last byte, if exist */ + if (cnt) { + count = 0; + data = *((FPWV *) wp); + + data = (data& 0x00ff) | (*src<< 8); + + if ((rc = write_word(info, (FPWV *) wp, data)) != 0) + return (rc); + cnt--; + } + + if (cnt == 0) + return ERR_OK; + + return ERR_OK; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash + * Function ready for 16 bit PS flash chips + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_word(flash_info_t * info, FPWV * dest, u16 data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest& data) != data) { + return (2); + } + + base = (FPWV *) (CONFIG_SYS_FLASH_BASE); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = 0xAA00; /* unlock */ + base[FLASH_CYCLE2] = 0x5500; /* unlock */ + base[FLASH_CYCLE1] = 0xA000; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + /* data polling for D7 */ + while (res == 0 +&& (*dest& 0x8000) != (data& 0x8000)) { + if (get_timer(start)> CONFIG_SYS_FLASH_WRITE_TOUT) { + *dest = 0xF000; /* reset bank */ + res = 1; + } + } + + *dest++ = 0xF000; /* reset bank */ + + return (res); +} + +void inline spin_wheel(void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} + +#endif diff --git a/board/sysam/amcore/u-boot.lds b/board/sysam/amcore/u-boot.lds new file mode 100644 index 0000000..ccb770d --- /dev/null +++ b/board/sysam/amcore/u-boot.lds @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2011 Angelo Dureghello<[email protected]> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + .text : + { + arch/m68k/cpu/mcf530x/start.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o (.text) + + *(.text) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF)& 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + KEEP(*(.got)) + __got_end = .; + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_)>>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.sdata) + } + _edata = .; + PROVIDE (edata = .); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + #include<u-boot.lst> + } + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + _sbss = .; + *(.sbss*) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + __bss_end__ = . ; + PROVIDE (end = .); +} diff --git a/boards.cfg b/boards.cfg index 0ecd1b8..536d048 100644 --- a/boards.cfg +++ b/boards.cfg @@ -375,6 +375,7 @@ M5271EVB m68k mcf52x2 m5271evb freesca M5272C3 m68k mcf52x2 m5272c3 freescale M5275EVB m68k mcf52x2 m5275evb freescale M5282EVB m68k mcf52x2 m5282evb freescale +amcore m68k mcf530x amcore sysam astro_mcf5373l m68k mcf532x mcf5373l astro M53017EVB m68k mcf532x m53017evb freescale M5329AFEE m68k mcf532x m5329evb freescale - M5329EVB:NANDFLASH_SIZE=0 diff --git a/include/configs/amcore.h b/include/configs/amcore.h new file mode 100644 index 0000000..c6b49e8 --- /dev/null +++ b/include/configs/amcore.h @@ -0,0 +1,193 @@ +/* + * Configuation settings for the Sysam AMCORE board. + * + * Copyright (c) 2011 Angelo Dureghello<[email protected]> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _AMCORE_H +#define _AMCORE_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF530x /* define processor family */ +#define CONFIG_M5307 /* define processor type */ + +#define CONFIG_MCFTMR + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } +#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_BOOTCOMMAND "bootm ffc20000" /* autoboot command */ + + + +#undef CONFIG_WATCHDOG +#undef CONFIG_MONITOR_IS_IN_RAM + +/* + * BOOTP options + */ +#undef CONFIG_BOOTP_BOOTFILESIZE +#undef CONFIG_BOOTP_BOOTPATH +#undef CONFIG_BOOTP_GATEWAY +#undef CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ + +#include<config_cmd_default.h> +#undef CONFIG_CMD_CACHE +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_CACHE + +#define CONFIG_SYS_PROMPT "amcore$ " +//#define CONFIG_SYS_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ + +#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ + +#undef CONFIG_SYS_DRAM_TEST +#define CONFIG_SYS_MEMTEST_START 0x0 +#define CONFIG_SYS_MEMTEST_END 0x100000 + +#define CONFIG_SYS_HZ 1000 + +/* + * Clock configuration: enable only one of the following options + */ + +#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ +#define CONFIG_SYS_CLK 90000000 /* MCF5307 run at 90MHz */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ + + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x600 /* Address of Environment Sector*/ +#define CONFIG_ENV_SIZE 0x0400 /* Total Size of Environment Sector */ +#define CONFIG_ENV_SECT_SIZE 0x0400 /* see README - env sector total size */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CONFIG_SYS_FLASH_BASE 0xffc00000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 + +#define FLASH_SST3201B 0x300 + +#define CONFIG_SYS_SST_SECT 1024 +#define CONFIG_SYS_SST_SECTSZ 0x1000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 + +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) + +#define CONFIG_SYS_MONITOR_LEN 0x20000 +#define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE<< 20)) + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ + CF_ADDRMASK(2) | \ + CF_ACR_EN | CF_ACR_SM_ALL) + +/* no ACR1 initialization for SDRAM before SDRAM init */ + +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ + +/* CS0 - AMD Flash, address 0xffc00000 */ +#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=10, AA=1, PS=16bit (10) */ +#define CONFIG_SYS_CS0_MASK 0x003f0001 /* 4MB, AA=0,V=1 C/I BIT !!!!! */ + +/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ +#define CONFIG_SYS_CS1_BASE 0x30000000 +#define CONFIG_SYS_CS1_CTRL 0x00000100 +#define CONFIG_SYS_CS1_MASK 0x00070001 + +#endif //_AMCORE_H diff --git a/include/flash.h b/include/flash.h index 7db599e..7b8bff0 100644 --- a/include/flash.h +++ b/include/flash.h @@ -282,6 +282,7 @@ extern flash_info_t *flash_get_info(ulong base); #define SST_ID_xF1601 0x234B234B /* 39xF1601 ID (16M = 1M x 16 ) */ #define SST_ID_xF1602 0x234A234A /* 39xF1602 ID (16M = 1M x 16 ) */ #define SST_ID_xF3201 0x235B235B /* 39xF3201 ID (32M = 2M x 16 ) */ +#define SST_ID_xF3201B 0x235D235D /* 39xF320B1 ID (32M = 2M x 16 ) */ #define SST_ID_xF3202 0x235A235A /* 39xF3202 ID (32M = 2M x 16 ) */ #define SST_ID_xF6401 0x236B236B /* 39xF6401 ID (64M = 4M x 16 ) */ #define SST_ID_xF6402 0x236A236A /* 39xF6402 ID (64M = 4M x 16 ) */ _______________________________________________ uClinux-dev mailing list [email protected] http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by [email protected] To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev