[PATCH 6/8] x86: require minimum 64 byte cache lines
Arnd Bergmann <[email protected]>
| Newsgroups | gmane.linux.uml.devel,gmane.linux.kernel |
|---|---|
| Message-ID | <[email protected]> |
From: Arnd Bergmann <[email protected]> Later x86-32 CPUs like Pentium-M, K7 and Atom use 64 byte cache lines and are incompatible with kernels built for smaller values of X86_L1_CACHE_SHIFT. Pentium-4 CPUs have 128 byte cache lines but are compatible with cache operations that expect the lines to be 64 bytes. Older CPUs have smaller cache lines of 16 or 32 bytes but work correctly when X86_L1_CACHE_SHIFT is set to a larger value. Remove the per-CPU tuning and always build for 64 or 128 byte cache lines that work correctly in any CPU. Signed-off-by: Arnd Bergmann <[email protected]> --- arch/x86/Kconfig.cpu | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 65d887274dd8..4991b633047e 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -180,8 +180,8 @@ config MVIAC7 bool "VIA C7" depends on X86_32 help - Select this for a VIA C7. Selecting this uses the correct cache - shift and tells gcc to treat the CPU as a 686. + Select this for a VIA C7. Selecting this tells gcc to treat the + CPU as a 686. config MATOM bool "Intel Atom" @@ -239,9 +239,7 @@ config X86_INTERNODE_CACHE_SHIFT config X86_L1_CACHE_SHIFT int default "7" if MPENTIUM4 - default "6" if MK7 || MPENTIUMM || MATOM || MVIAC7 || X86_GENERIC || X86_64 - default "4" if MGEODEGX1 - default "5" if MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MVIAC3_2 || MGEODE_LX + default "6" config X86_F00F_BUG def_bool y -- 2.39.5