Re: [PATCH v2 2/8] um: Check for missing AVX and AVX-512 xstate bits
Borislav Petkov <[email protected]> Thu, 30 Jul 2026 16:06:37 -0700
| Newsgroups | gmane.linux.uml.devel,gmane.linux.raid,gmane.linux.kernel.cryptoapi,gmane.linux.kernel |
|---|---|
| Message-ID | <20260730230637.GKamvY_aj0Uxn8Dshs@fat_crate.local> |
On Mon, Jul 27, 2026 at 07:15:57PM -0700, Eric Biggers wrote: > If the CPU declares AVX or AVX-512 support, verify that all the > corresponding bits are set in the XCR0 register. If any are missing, > warn and don't set the corresponding X86_FEATURE_* flags. > > This eliminates the perceived need for UML-supporting AVX and AVX-512 > optimized code in the kernel (that is, lib/raid/ currently) to start > checking the XCR0 bits in addition to X86_FEATURE_AVX*. > > This aligns UML with the vast majority of userspace programs, which > check the XCR0 bits before considering AVX and AVX-512 to be supported, > as per the procedure documented in Intel's CPU manual. > > Signed-off-by: Eric Biggers <[email protected]> > --- > arch/um/kernel/um_arch.c | 78 +++++++++++++++++++++++++++++++++++++++- > 1 file changed, 77 insertions(+), 1 deletion(-) ./scripts/get_maintainer.pl -f arch/um/kernel/um_arch.c Richard Weinberger <[email protected]> (maintainer:USER-MODE LINUX (UML)) Anton Ivanov <[email protected]> (maintainer:USER-MODE LINUX (UML)) Johannes Berg <[email protected]> (maintainer:USER-MODE LINUX (UML),commit_signer:8/10=80%,authored:1/10=10%,removed_lines:2/40=5%) ... Please use that script. CCed now. > diff --git a/arch/um/kernel/um_arch.c b/arch/um/kernel/um_arch.c > index 2141f5f1f5a20..aafbaef2ae82f 100644 > --- a/arch/um/kernel/um_arch.c > +++ b/arch/um/kernel/um_arch.c > @@ -264,12 +264,88 @@ unsigned long brk_start; > > #define MIN_VMALLOC (32 * 1024 * 1024) > > +static u64 __init read_xcr0(void) > +{ > + u32 a, b, c, d; > + > + asm volatile("cpuid" > + : "=a"(a), "=b"(b), "=c"(c), "=d"(d) > + : "a"(0), "c"(0)); > + if (a >= 1) { /* max_leaf >= 1 */ > + asm volatile("cpuid" > + : "=a"(a), "=b"(b), "=c"(c), "=d"(d) > + : "a"(1), "c"(0)); > + if (c & (1 << 27)) { /* XSAVE enabled by OS */ > + asm volatile("xgetbv" : "=d"(d), "=a"(a) : "c"(0)); > + return ((u64)d << 32) | a; > + } > + } I don't know - I probably would pull in some helpers for cpuid and xgetbv instead of doing this ad-hoc. UML maintainers' call. > + return 0; > +} Thx. -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette