Re: Fwd: Re: PXA27x UDC driver GIT repository

 Hi Rodolfo,

 This solution works for me too but I do not see much sense in such a 
modification: my approach clears SST before breaking the for-loop, your 
approach does this after breaking the for-loop. If something goes wrong and 
the for-loop comes to its logical end without breaking then SST is clear, so 
resetting it in your approach does change nothing. Am I missed something ?

 Regards, Yuri

On Tuesday 04 September 2007 18:50, Rodolfo Giometti wrote:
...
> It seems to me that after setting FST bit in order to force a STALL,
> the driver waits for SST bit assert that means the STALL handshake has
> actually been sent to the USB host controller and the STALL state
> entered.
>
> That's why I think that we should clear SST bit _after_ the "for"
> cycle ends. That is:
>
> 	/* FST bit is the same for control, bulk in, bulk out, interrupt in */
> 	*ep->reg_udccsr = UDCCSR_FST | UDCCSR_FEF;
>
>         /* ep0 needs special care */
> 	if (!ep->desc) {
>                 start_udc_watchdog(ep->udc);
>                 ep->udc->req_pending = 0;
>                 ep->udc->ep0state = EP0_STALL;
>
> 		/* and bulk/intr endpoints like dropping stalls too */
> 	} else {
>                 unsigned i;
> 		for (i = 0; i < 1000; i += 20) {
> 			if (*ep->reg_udccsr & UDCCSR_SST)
> 				break;
> 			udelay(20);
> 		}
> +
> +               /* According to UM we must clear the SST bit
> +                * before the USB host controller requests more
> +                * data from IN endpoints; do it right now.
> +                */
> +               *ep->reg_udccsr = UDCCSR_SST;
>
> 	}
>
> What do you think about that? Can you please test this solution also?
> I'm very busy now and I cannot do it myself.
>
> Thanks,

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