Re: Performance assistance / advice
"Yuri Davidovsky (as work at disclosure dot ie)" <[email protected]>
| Newsgroups | gmane.lisp.lispworks.general |
|---|---|
| Message-ID | <[email protected]> |
> On 11 Mar 2025, at 16:52, Tim Bradshaw (as tfb at tfeb dot org) <[email protected]> wrote: > > I'm not sure if these rates are plausible or not: I think they probably are: The M1 seems to be clocked at 3.2GHz and assuming 4 cores the SBCL unsafe rate is 2.1 FLOP/cycle/core which, given it's a superscalar processor, is plausible. Not 100% sure but that may look off. Getting multiples of the clock speed without vectorisation might be pointing to something strange going on. Now, there is a fused multiply add instruction on arm64 (a * b + c) that combines 2 operations into one, which in theory may give you the stated ~2x increase per cycle in sbcl if you have plenty of such operations, but you have more than 2x operations per cycle, evidently. There may be some other similar instructions that I am not aware of, or sbcl is doing some low key vectorisation. Most likely there is some compiler optimisation going on, which may, or may not be what you want here (I understand that you wanted to measure purely scalar performance), in which case non vectorised fma is fine if that is what is happening. _______________________________________________ Lisp Hug - the mailing list for LispWorks users [email protected] http://www.lispworks.com/support/lisp-hug.html