master: arm64: encode more vector shift instructions

The branch "master" has been updated in SBCL:
       via  6927ec50b9de0149b087bccfddc3cf5e2679288d (commit)
      from  809276aeddf54a89ac830d151010089198cf2745 (commit)

- Log -----------------------------------------------------------------
commit 6927ec50b9de0149b087bccfddc3cf5e2679288d
Author: Stas Boukarev <[email protected]>
Date:   Mon Jul 13 23:19:41 2026 +0300

    arm64: encode more vector shift instructions
---
 src/compiler/arm64/insts.lisp | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/compiler/arm64/insts.lisp b/src/compiler/arm64/insts.lisp
index 4249591b6..590f2ca23 100644
--- a/src/compiler/arm64/insts.lisp
+++ b/src/compiler/arm64/insts.lisp
@@ -4236,9 +4236,17 @@
   (def shl #b0 #b01010 nil t)
   (def sli #b1 #b01010)
   (def sri #b1 #b01000 t)
-  (def ushr #b1 #b00000 t t)
   (def sshr #b0 #b00000 t t)
-  (def shrn #b0 #b10000 t))
+  (def shrn #b0 #b10000 t)
+  (def ssra #b0 #b00010 t t)
+  (def srshr #b0 #b00100 t t)
+  (def srsra #b0 #b00110 t t)
+  (def ushr #b1 #b00000 t t)
+  (def usra #b1 #b00010 t t)
+  (def urshr #b1 #b00100 t t)
+  (def ursra #b1 #b00110 t t)
+  (def sqshlu #b1 #b01100 nil t)
+  (def uqshrn #b1 #b10010 t t))
 
 (def-emitter simd-modified-imm
   (#b0 1 31)

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