Re: [Sbcl-bugs] [PATCH] Properly model the non-existing floating point traps on RISC-V

Applied. Thanks

On Wed, Feb 11, 2026 at 6:55 PM Andreas Schwab <[email protected]> wrote:
>
>
> ---
>  src/compiler/riscv/parms.lisp | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/compiler/riscv/parms.lisp b/src/compiler/riscv/parms.lisp
> index e05b33301..a41685d62 100644
> --- a/src/compiler/riscv/parms.lisp
> +++ b/src/compiler/riscv/parms.lisp
> @@ -51,7 +51,7 @@
>  (defconstant-eqx float-rounding-mode (byte 3 5) #'equalp)
>  (defconstant-eqx float-sticky-bits (byte 5 0) #'equalp)
>  ;;;; RISC-V has no explicit floating point traps.
> -(defconstant-eqx float-traps-byte (byte 5 0) #'equalp)
> +(defconstant-eqx float-traps-byte (byte 0 0) #'equalp)
>  (defconstant-eqx float-exceptions-byte (byte 5 0) #'equalp)
>  (defconstant float-fast-bit (ash 1 24)) ;; Flush-to-zero mode
>
> --
> 2.52.0
>
>
> --
> Andreas Schwab, SUSE Labs, [email protected]
> GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
> "And now for something completely different."
>
>
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> Sbcl-bugs mailing list
> [email protected]
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