Re: [patch] Two Intel ADX instructions

Stas Boukarev <[email protected]> Sun, 1 Mar 2026 22:18:52 +0300
Newsgroups gmane.lisp.steel-bank.devel
Message-ID <CAF63=131oJGX=wUHZQenUAPzC8ZHWentWO+6DYb3EUByukZddQ@mail.gmail.com>
Applied. Thanks.

On Sun, Mar 1, 2026 at 10:11 PM Robert Smith <[email protected]> wrote:
>
> Hello SBCL friends:
>
> Attached is a patch to add ADCX and ADOX to SBCL's assembler. It
> doesn't change any VOPs. It's a very small patch, but I'm not sure if
> I got a few things right. Some points:
>
> - The ADX extension isn't supported by all processors. Support began
> on AMD Ryzen and Intel Broadwell (both ~10 years ago, plus or minus).
> Since this is "recent", I decided to put these instruction definitions
> next to their closest cousin, MULX, in the AVX2 file. (Technically
> MULX is from the BMI2, too.)
>
> - There is a CPUID way to determine support, but I felt getting into
> the weeds of config and build for this granular addition was too much,
> so I instead rely on AVX2 "implying" ADX.
>
> - The tests are just a couple smoke tests, nothing too serious.
>
> - I'm not an expert at x86 instruction encodings, so I did a little
> bit of mimicry + referencing section 10.5 of [1].
>
> - I've tested these instructions in an "actual" application that uses
> these paths billions of times in a tedious arithmetic calculation with
> verified intermediate and final results.
>
> This patch allows me to write faster code for extremely high-precision
> arithmetic beyond SBCL BIGNUM and GMP, specifically for add-mul-carry
> chains that occur in large integer multiplication and a few other
> places. While it's a welcome improvement in many regards, it's not
> critical, so I will not be offended in the slightest if this patch is
> turned away. :)
>
> Robert
>
> [1] https://web.archive.org/web/20130929035331/http://download-software.intel.com/sites/default/files/319433-015.pdf
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