Re: [Sbcl-commits] master: arm64-arch.c: Fix soft-simulation of some instructions.
Charles Zhang via Sbcl-devel <[email protected]> Wed, 20 May 2026 21:22:11 +0000 (UTC)
| Newsgroups | gmane.lisp.steel-bank.devel |
|---|---|
| Message-ID | <[email protected]> |
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Thanks. Not a proper fix because I don't have a Windows machine. I'm thorou=
ghly confused about why this is Windows only.
=20
On Wednesday, May 20, 2026 at 08:29:14 PM GMT+2, Stas Boukarev <stassat=
[email protected]> wrote: =20
=20
::: Running (TRACE :ENCAPSULATE NIL)
fatal error encountered in SBCL pid 5521255184:
Unsupported LDR (literal) variant.
0: 00000291caaa1938 pc=3D0000001000181ed0 {0000001000181dc0+0110}
SB-DI::BREAKPOINT-DO-DISPLACED-INST
1: 00000291caaa1928 pc=3D00007ff7531059e0
2: 00000291caaa1900 pc=3D00000010019d75e0 {00000010019d7580+0060}
CL-USER::TRACE-THIS
On Wed, May 20, 2026 at 1:14=E2=80=AFPM apache--- via Sbcl-commits
<[email protected]> wrote:
>
> The branch "master" has been updated in SBCL:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 via=C2=A0 f982475b0bcb6d691cf172630fad9c140873=
78b2 (commit)
>=C2=A0 =C2=A0 =C2=A0 from=C2=A0 07f82d35917900fe1222891579c2fe9d3d8df3c4 (=
commit)
>
> - Log -----------------------------------------------------------------
> commit f982475b0bcb6d691cf172630fad9c14087378b2
> Author: Charles Zhang <[email protected]>
> Date:=C2=A0 Tue Mar 17 15:18:20 2026 +0100
>
>=C2=A0 =C2=A0 arm64-arch.c: Fix soft-simulation of some instructions.
>
>=C2=A0 =C2=A0 For breakpoint support.
> ---
>=C2=A0 src/runtime/arm64-arch.c | 63 ++++++++++++++++++++++++++++++-------=
-----------
>=C2=A0 1 file changed, 39 insertions(+), 24 deletions(-)
>
> diff --git a/src/runtime/arm64-arch.c b/src/runtime/arm64-arch.c
> index 9183013fe..e9e8d3af1 100644
> --- a/src/runtime/arm64-arch.c
> +++ b/src/runtime/arm64-arch.c
> @@ -88,20 +88,35 @@ condition_holds(os_context_t *context, unsigned int c=
ond)
>=C2=A0 {
>=C2=A0 =C2=A0 =C2=A0 int flags =3D *os_context_flags_addr(context);
>=C2=A0 =C2=A0 =C2=A0 bool result;
> -=C2=A0 =C2=A0 // Evaluate base condition.
> -=C2=A0 =C2=A0 switch (cond) {
> -=C2=A0 =C2=A0 case 0b000: result =3D ((flags >> Z_BIT) & 1);
> -=C2=A0 =C2=A0 case 0b001: result =3D ((flags >> C_BIT) & 1);
> -=C2=A0 =C2=A0 case 0b010: result =3D ((flags >> N_BIT) & 1);
> -=C2=A0 =C2=A0 case 0b011: result =3D ((flags >> V_BIT) & 1);
> -=C2=A0 =C2=A0 case 0b100: result =3D ((flags >> V_BIT) & 1) && ~((flags =
>> Z_BIT) & 1);
> -=C2=A0 =C2=A0 case 0b101: result =3D ((flags >> N_BIT) =3D=3D (flags >> =
V_BIT));
> -=C2=A0 =C2=A0 case 0b110: result =3D ((flags >> N_BIT) =3D=3D (flags >> =
V_BIT)) && !((flags >> Z_BIT) & 1);
> -=C2=A0 =C2=A0 case 0b111: result =3D 1;
> +=C2=A0 =C2=A0 // Evaluate base condition (ignoring the inversion bit).
> +=C2=A0 =C2=A0 switch (cond >> 1) {
> +=C2=A0 =C2=A0 case 0b000:
> +=C2=A0 =C2=A0 =C2=A0 result =3D (flags >> Z_BIT) & 1;
> +=C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case 0b001:
> +=C2=A0 =C2=A0 =C2=A0 result =3D (flags >> C_BIT) & 1;
> +=C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case 0b010:
> +=C2=A0 =C2=A0 =C2=A0 result =3D (flags >> N_BIT) & 1;
> +=C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case 0b011: result =3D (flags >> V_BIT) & 1;
> +=C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case 0b100:
> +=C2=A0 =C2=A0 =C2=A0 result =3D ((flags >> C_BIT) & 1) && !((flags >> Z_=
BIT) & 1);
> +=C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case 0b101:
> +=C2=A0 =C2=A0 =C2=A0 result =3D ((flags >> N_BIT) & 1) =3D=3D ((flags >>=
V_BIT) & 1);
> +=C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 case 0b110:
> +=C2=A0 =C2=A0 =C2=A0 result =3D ((flags >> N_BIT) & 1) =3D=3D ((flags >>=
V_BIT) & 1) && !((flags >> Z_BIT) & 1);
> +=C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 default:
> +=C2=A0 =C2=A0 =C2=A0 result =3D 1;
> +=C2=A0 =C2=A0 =C2=A0 break;
>=C2=A0 =C2=A0 =C2=A0 }
>
> -=C2=A0 =C2=A0 // Condition flag values in the set '111x' indicate always=
true
> -=C2=A0 =C2=A0 // Otherwise, invert condition if necessary.
> +=C2=A0 =C2=A0 // Condition flag values in the set '111x' indicate always=
true.
> +=C2=A0 =C2=A0 // Otherwise, invert condition if the low bit is set.
>=C2=A0 =C2=A0 =C2=A0 if ((cond & 0b1) && (cond !=3D 0b1111))
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 result =3D !result;
>
> @@ -158,12 +173,10 @@ void arch_do_displaced_inst(os_context_t *context, =
unsigned int orig_inst)
>=C2=A0 =C2=A0 =C2=A0 }
>=C2=A0 =C2=A0 =C2=A0 else if (((orig_inst >> 25) & 0b111111) =3D=3D 0b0110=
10) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 // Compare branch imm
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 bool size_is_64 =3D (orig_inst >> 31) & 0b1;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bool op =3D (orig_inst >> 24) & 0b1;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int offset =3D sign_extend((orig_inst >=
> 5) & ~(1 << 19), 19);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int rt =3D orig_inst & 0b11111;
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!size_is_64) lose("Size must be 64 bits.=
");
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (*os_context_register_addr(context, rt) ^=
op)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if ((!*os_context_register_addr(context, rt)=
) ^ op)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 next_pc +=3D offset;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 else
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 next_pc +=3D 1;
> @@ -173,32 +186,34 @@ void arch_do_displaced_inst(os_context_t *context, =
unsigned int orig_inst)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bool b5 =3D (orig_inst >> 31) & 0b1;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bool op =3D (orig_inst >> 24) & 0b1;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bool b40 =3D (orig_inst >> 19) & 0b1111=
1;
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 int bit_pos =3D (b5 << 6) | b40;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 int bit_pos =3D (b5 << 5) | b40;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int offset =3D sign_extend((orig_inst >=
> 5) & ~(1 << 14), 14);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int rt =3D orig_inst & 0b11111;
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!b5) lose("b5 must be 64 bits.");
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (((*os_context_register_addr(context=
, rt) >> bit_pos) & 0b1) ^ op)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 next_pc +=3D offset;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 else
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 next_pc +=3D 1;
>=C2=A0 =C2=A0 =C2=A0 }
> -=C2=A0 =C2=A0 else if (((orig_inst >> 31) & 0b1) =3D=3D 0b0) {
> +=C2=A0 =C2=A0 else if (((orig_inst >> 24) & 0b11111) =3D=3D 0b11000) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 // LDR (literal)
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 bool size_is_64 =3D (orig_inst >> 30) & 0b1;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 int opc =3D (orig_inst >> 30) & 0b11;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int rt =3D orig_inst & 0b11111;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int offset =3D sign_extend((orig_inst >=
> 5) & ~(1 << 19), 19);
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!size_is_64) lose("Size must be 64 bits.=
");
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 *os_context_register_addr(context, rt) =3D *=
((lispobj*)(pc + offset));
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (opc =3D=3D 0b01)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *os_context_register_addr(context, rt=
) =3D *((uint64_t *)(pc + offset));
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 else if (opc =3D=3D 0b00)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *os_context_register_addr(context, rt=
) =3D *((uint32_t *)(pc + offset));
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 else
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 lose("Unsupported LDR (literal) varia=
nt.");
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 next_pc +=3D 1;
>=C2=A0 =C2=A0 =C2=A0 }
>=C2=A0 =C2=A0 =C2=A0 else if (((orig_inst >> 24) & 0b11111) =3D=3D 0b10000=
) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 // ADR(P)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bool op =3D (orig_inst >> 31) & 0b1;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int rd =3D orig_inst & 0b11111;
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 int imm =3D sign_extend(((orig_inst >> 5) & =
~(1 << 19)) |
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ((orig_inst >> 29) & ~(1 << 2)), 21);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 int imm =3D sign_extend(((orig_inst >> 3) & =
0x1FFFFC) | ((orig_inst >> 29) & 3), 21);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (op) // ADRP
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *os_context_register_addr(cont=
ext, rd) =3D ((uword_t)pc & ~(1 << 12)) + (imm << 12);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *os_context_register_addr(cont=
ext, rd) =3D ((uword_t)pc & ~(uword_t)0xFFF) + ((sword_t)imm << 12);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 else // ADR
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *os_context_register_addr=
(context, rd) =3D (uword_t)pc + imm;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 next_pc +=3D 1;
>
> -----------------------------------------------------------------------
>
>
> hooks/post-receive
> --
> SBCL
>
>
> _______________________________________________
> Sbcl-commits mailing list
> [email protected]
> https://lists.sourceforge.net/lists/listinfo/sbcl-commits
=20
------=_Part_4006311_1945913345.1779312131522
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: quoted-printable
<html><head></head><body><div class=3D"ydp4b307be1yahoo-style-wrap" style=
=3D"font-family:Helvetica Neue, Helvetica, Arial, sans-serif;font-size:16px=
;"><div><div dir=3D"ltr" data-setdir=3D"false">Thanks. Not a proper fix bec=
ause I don't have a Windows machine. I'm thoroughly confused about why this=
is Windows only.</div><div><br></div><div class=3D"ydp4b307be1signature"><=
div><span style=3D"font-size:16px;"><span style=3D"color:rgb(0, 191, 191);"=
><span style=3D"font-family:arial, helvetica, sans-serif;"><span id=3D"ydp4=
b307be1result_box" lang=3D"la" class=3D"ydp4b307be1short_text"><span></span=
></span></span><span style=3D"font-size:16px;"><span style=3D"color:rgb(0, =
191, 191);"><span id=3D"ydp4b307be1result_box" lang=3D"el" class=3D"ydp4b30=
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le=3D"color:rgb(0, 191, 191);"><br></span><span style=3D"font-size:16px;"><=
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ang=3D"el" class=3D"ydp4b307be1short_text"><span class=3D"ydp4b307be1hps"><=
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07be1short_text"><span class=3D"ydp4b307be1hps"></span></span></span><br></=
span></div></div></div>
<div><br></div><div><br></div>
=20
</div><div id=3D"ydp70fab57ayahoo_quoted_9823886147" class=3D"ydp70=
fab57ayahoo_quoted">
<div style=3D"font-family:'Helvetica Neue', Helvetica, Arial, s=
ans-serif;font-size:13px;">
=20
<div>
On Wednesday, May 20, 2026 at 08:29:14 PM GMT+2, Stas B=
oukarev <[email protected]> wrote:
</div>
<div><br></div>
<div><br></div>
<div><div dir=3D"ltr">::: Running (TRACE :ENCAPSULATE NIL)<=
br></div><div dir=3D"ltr">fatal error encountered in SBCL pid 5521255184:<b=
r></div><div dir=3D"ltr">Unsupported LDR (literal) variant.<br></div><div d=
ir=3D"ltr">0: 00000291caaa1938 pc=3D0000001000181ed0 {0000001000181dc0+0110=
}<br></div><div dir=3D"ltr">SB-DI::BREAKPOINT-DO-DISPLACED-INST<br></div><d=
iv dir=3D"ltr">1: 00000291caaa1928 pc=3D00007ff7531059e0<br></div><div dir=
=3D"ltr">2: 00000291caaa1900 pc=3D00000010019d75e0 {00000010019d7580+0060}<=
br></div><div dir=3D"ltr">CL-USER::TRACE-THIS<br></div><div dir=3D"ltr"><br=
></div><div dir=3D"ltr">On Wed, May 20, 2026 at 1:14=E2=80=AFPM apache--- v=
ia Sbcl-commits<br></div><div dir=3D"ltr"><<a href=3D"mailto:sbcl-commit=
[email protected]" rel=3D"nofollow" target=3D"_blank">sbcl-commits@li=
sts.sourceforge.net</a>> wrote:<br></div><div dir=3D"ltr">><br></div>=
<div dir=3D"ltr">> The branch "master" has been updated in SBCL:<br></di=
v><div dir=3D"ltr">> via f982475b0bcb6d=
691cf172630fad9c14087378b2 (commit)<br></div><div dir=3D"ltr">> &n=
bsp; from 07f82d35917900fe1222891579c2fe9d3d8df3c4 (commit)<b=
r></div><div dir=3D"ltr">><br></div><div dir=3D"ltr">> - Log --------=
---------------------------------------------------------<br></div><div dir=
=3D"ltr">> commit f982475b0bcb6d691cf172630fad9c14087378b2<br></div><div=
dir=3D"ltr">> Author: Charles Zhang <<a href=3D"mailto:charleszhang9=
[email protected]" rel=3D"nofollow" target=3D"_blank">[email protected]</a=
>><br></div><div dir=3D"ltr">> Date: Tue Mar 17 15:18:20 2026 =
+0100<br></div><div dir=3D"ltr">><br></div><div dir=3D"ltr">> &=
nbsp; arm64-arch.c: Fix soft-simulation of some instructions.<br></div><di=
v dir=3D"ltr">><br></div><div dir=3D"ltr">> For breakpo=
int support.<br></div><div dir=3D"ltr">> ---<br></div><div dir=3D"ltr">&=
gt; src/runtime/arm64-arch.c | 63 ++++++++++++++++++++++++++++++-----=
-------------<br></div><div dir=3D"ltr">> 1 file changed, 39 inser=
tions(+), 24 deletions(-)<br></div><div dir=3D"ltr">><br></div><div dir=
=3D"ltr">> diff --git a/src/runtime/arm64-arch.c b/src/runtime/arm64-arc=
h.c<br></div><div dir=3D"ltr">> index 9183013fe..e9e8d3af1 100644<br></d=
iv><div dir=3D"ltr">> --- a/src/runtime/arm64-arch.c<br></div><div dir=
=3D"ltr">> +++ b/src/runtime/arm64-arch.c<br></div><div dir=3D"ltr">>=
@@ -88,20 +88,35 @@ condition_holds(os_context_t *context, unsigned int co=
nd)<br></div><div dir=3D"ltr">> {<br></div><div dir=3D"ltr">>&n=
bsp; int flags =3D *os_context_flags_addr(context);<br></div>=
<div dir=3D"ltr">> bool result;<br></div><div dir=3D=
"ltr">> - // Evaluate base condition.<br></div><div dir=3D"=
ltr">> - switch (cond) {<br></div><div dir=3D"ltr">> -&n=
bsp; case 0b000: result =3D ((flags >> Z_BIT) & 1);<br></d=
iv><div dir=3D"ltr">> - case 0b001: result =3D ((flags >=
> C_BIT) & 1);<br></div><div dir=3D"ltr">> - case 0b=
010: result =3D ((flags >> N_BIT) & 1);<br></div><div dir=3D"ltr"=
>> - case 0b011: result =3D ((flags >> V_BIT) & 1=
);<br></div><div dir=3D"ltr">> - case 0b100: result =3D ((f=
lags >> V_BIT) & 1) && ~((flags >> Z_BIT) & 1);=
<br></div><div dir=3D"ltr">> - case 0b101: result =3D ((fla=
gs >> N_BIT) =3D=3D (flags >> V_BIT));<br></div><div dir=3D"ltr=
">> - case 0b110: result =3D ((flags >> N_BIT) =3D=3D=
(flags >> V_BIT)) && !((flags >> Z_BIT) & 1);<br><=
/div><div dir=3D"ltr">> - case 0b111: result =3D 1;<br></di=
v><div dir=3D"ltr">> + // Evaluate base condition (ignoring=
the inversion bit).<br></div><div dir=3D"ltr">> + switch (=
cond >> 1) {<br></div><div dir=3D"ltr">> + case 0b000=
:<br></div><div dir=3D"ltr">> + result =3D (flags &g=
t;> Z_BIT) & 1;<br></div><div dir=3D"ltr">> + =
break;<br></div><div dir=3D"ltr">> + case 0b001:<br></div>=
<div dir=3D"ltr">> + result =3D (flags >> C_BI=
T) & 1;<br></div><div dir=3D"ltr">> + break;<br>=
</div><div dir=3D"ltr">> + case 0b010:<br></div><div dir=3D=
"ltr">> + result =3D (flags >> N_BIT) & 1;=
<br></div><div dir=3D"ltr">> + break;<br></div><div =
dir=3D"ltr">> + case 0b011: result =3D (flags >> V_BI=
T) & 1;<br></div><div dir=3D"ltr">> + break;<br>=
</div><div dir=3D"ltr">> + case 0b100:<br></div><div dir=3D=
"ltr">> + result =3D ((flags >> C_BIT) & 1=
) && !((flags >> Z_BIT) & 1);<br></div><div dir=3D"ltr">&=
gt; + break;<br></div><div dir=3D"ltr">> + &nb=
sp; case 0b101:<br></div><div dir=3D"ltr">> + result=
=3D ((flags >> N_BIT) & 1) =3D=3D ((flags >> V_BIT) & =
1);<br></div><div dir=3D"ltr">> + break;<br></div><d=
iv dir=3D"ltr">> + case 0b110:<br></div><div dir=3D"ltr">&g=
t; + result =3D ((flags >> N_BIT) & 1) =3D=3D=
((flags >> V_BIT) & 1) && !((flags >> Z_BIT) &=
1);<br></div><div dir=3D"ltr">> + break;<br></div><=
div dir=3D"ltr">> + default:<br></div><div dir=3D"ltr">>=
+ result =3D 1;<br></div><div dir=3D"ltr">> + =
break;<br></div><div dir=3D"ltr">> }<=
br></div><div dir=3D"ltr">><br></div><div dir=3D"ltr">> -  =
; // Condition flag values in the set '111x' indicate always true<br></div>=
<div dir=3D"ltr">> - // Otherwise, invert condition if nece=
ssary.<br></div><div dir=3D"ltr">> + // Condition flag valu=
es in the set '111x' indicate always true.<br></div><div dir=3D"ltr">> +=
// Otherwise, invert condition if the low bit is set.<br></di=
v><div dir=3D"ltr">> if ((cond & 0b1) &&=
(cond !=3D 0b1111))<br></div><div dir=3D"ltr">> &nb=
sp; result =3D !result;<br></div><div dir=3D"ltr">><br></div><div=
dir=3D"ltr">> @@ -158,12 +173,10 @@ void arch_do_displaced_inst(os_cont=
ext_t *context, unsigned int orig_inst)<br></div><div dir=3D"ltr">> =
; }<br></div><div dir=3D"ltr">> else i=
f (((orig_inst >> 25) & 0b111111) =3D=3D 0b011010) {<br></div><di=
v dir=3D"ltr">> // Compare branch imm<=
br></div><div dir=3D"ltr">> - bool size_is_64=
=3D (orig_inst >> 31) & 0b1;<br></div><div dir=3D"ltr">> =
; bool op =3D (orig_inst >> 24) & 0b1=
;<br></div><div dir=3D"ltr">> int offs=
et =3D sign_extend((orig_inst >> 5) & ~(1 << 19), 19);<br><=
/div><div dir=3D"ltr">> int rt =3D ori=
g_inst & 0b11111;<br></div><div dir=3D"ltr">> - =
if (!size_is_64) lose("Size must be 64 bits.");<br></div><div dir=3D=
"ltr">> - if (*os_context_register_addr(conte=
xt, rt) ^ op)<br></div><div dir=3D"ltr">> + i=
f ((!*os_context_register_addr(context, rt)) ^ op)<br></div><div dir=3D"ltr=
">> next_pc +=3D offset;=
<br></div><div dir=3D"ltr">> else<br><=
/div><div dir=3D"ltr">> =
next_pc +=3D 1;<br></div><div dir=3D"ltr">> @@ -173,32 +186,34 @@ void a=
rch_do_displaced_inst(os_context_t *context, unsigned int orig_inst)<br></d=
iv><div dir=3D"ltr">> bool b5 =3D (ori=
g_inst >> 31) & 0b1;<br></div><div dir=3D"ltr">> =
bool op =3D (orig_inst >> 24) & 0b1;<br></di=
v><div dir=3D"ltr">> bool b40 =3D (ori=
g_inst >> 19) & 0b11111;<br></div><div dir=3D"ltr">> - &=
nbsp; int bit_pos =3D (b5 << 6) | b40;<br></div><div di=
r=3D"ltr">> + int bit_pos =3D (b5 << 5)=
| b40;<br></div><div dir=3D"ltr">> in=
t offset =3D sign_extend((orig_inst >> 5) & ~(1 << 14), 14)=
;<br></div><div dir=3D"ltr">> int rt =
=3D orig_inst & 0b11111;<br></div><div dir=3D"ltr">> - =
if (!b5) lose("b5 must be 64 bits.");<br></div><div dir=3D"lt=
r">> if (((*os_context_register_addr(c=
ontext, rt) >> bit_pos) & 0b1) ^ op)<br></div><div dir=3D"ltr">&g=
t; next_pc +=3D offset;<br>=
</div><div dir=3D"ltr">> else<br></div=
><div dir=3D"ltr">> next=
_pc +=3D 1;<br></div><div dir=3D"ltr">> }<br></div><=
div dir=3D"ltr">> - else if (((orig_inst >> 31) &=
0b1) =3D=3D 0b0) {<br></div><div dir=3D"ltr">> + else if (=
((orig_inst >> 24) & 0b11111) =3D=3D 0b11000) {<br></div><div dir=
=3D"ltr">> // LDR (literal)<br></div><=
div dir=3D"ltr">> - bool size_is_64 =3D (orig=
_inst >> 30) & 0b1;<br></div><div dir=3D"ltr">> + =
int opc =3D (orig_inst >> 30) & 0b11;<br></div><di=
v dir=3D"ltr">> int rt =3D orig_inst &=
amp; 0b11111;<br></div><div dir=3D"ltr">> &nb=
sp; int offset =3D sign_extend((orig_inst >> 5) & ~(1 << 19=
), 19);<br></div><div dir=3D"ltr">> - if (!si=
ze_is_64) lose("Size must be 64 bits.");<br></div><div dir=3D"ltr">> -&n=
bsp; *os_context_register_addr(context, rt) =3D *((lis=
pobj*)(pc + offset));<br></div><div dir=3D"ltr">> + =
if (opc =3D=3D 0b01)<br></div><div dir=3D"ltr">> + &=
nbsp; *os_context_register_addr(context, rt) =3D *((uint64_t =
*)(pc + offset));<br></div><div dir=3D"ltr">> + &nbs=
p; else if (opc =3D=3D 0b00)<br></div><div dir=3D"ltr">> + =
*os_context_register_addr(context, rt) =3D *((uint32_t=
*)(pc + offset));<br></div><div dir=3D"ltr">> + &nb=
sp; else<br></div><div dir=3D"ltr">> + =
lose("Unsupported LDR (literal) variant.");<br></div><div dir=3D"ltr">>=
next_pc +=3D 1;<br></div><div dir=3D"ltr=
">> }<br></div><div dir=3D"ltr">> &n=
bsp; else if (((orig_inst >> 24) & 0b11111) =3D=3D 0b10000) {<br>=
</div><div dir=3D"ltr">> // ADR(P)<br>=
</div><div dir=3D"ltr">> bool op =3D (=
orig_inst >> 31) & 0b1;<br></div><div dir=3D"ltr">> &nbs=
p; int rd =3D orig_inst & 0b11111;<br></div><div d=
ir=3D"ltr">> - int imm =3D sign_extend(((orig=
_inst >> 5) & ~(1 << 19)) |<br></div><div dir=3D"ltr">> =
- &nbs=
p; ((orig_inst >> 29) & ~(1 << =
2)), 21);<br></div><div dir=3D"ltr">> + int i=
mm =3D sign_extend(((orig_inst >> 3) & 0x1FFFFC) | ((orig_inst &g=
t;> 29) & 3), 21);<br></div><div dir=3D"ltr">>  =
; if (op) // ADRP<br></div><div dir=3D"ltr">> - &nbs=
p; *os_context_register_addr(context, rd) =3D (=
(uword_t)pc & ~(1 << 12)) + (imm << 12);<br></div><div dir=
=3D"ltr">> + *os_context_regist=
er_addr(context, rd) =3D ((uword_t)pc & ~(uword_t)0xFFF) + ((sword_t)im=
m << 12);<br></div><div dir=3D"ltr">> &=
nbsp; else // ADR<br></div><div dir=3D"ltr">> =
*os_context_register_addr(context, rd) =3D (uword_t)p=
c + imm;<br></div><div dir=3D"ltr">> n=
ext_pc +=3D 1;<br></div><div dir=3D"ltr">><br></div><div dir=3D"ltr">>=
; -----------------------------------------------------------------------<b=
r></div><div dir=3D"ltr">><br></div><div dir=3D"ltr">><br></div><div =
dir=3D"ltr">> hooks/post-receive<br></div><div dir=3D"ltr">> --<br></=
div><div dir=3D"ltr">> SBCL<br></div><div dir=3D"ltr">><br></div><div=
dir=3D"ltr">><br></div><div dir=3D"ltr">> __________________________=
_____________________<br></div><div dir=3D"ltr">> Sbcl-commits mailing l=
ist<br></div><div dir=3D"ltr">> <a href=3D"mailto:[email protected]=
rceforge.net" rel=3D"nofollow" target=3D"_blank">[email protected]=
orge.net</a><br></div><div dir=3D"ltr">> <a href=3D"https://lists.source=
forge.net/lists/listinfo/sbcl-commits" rel=3D"nofollow" target=3D"_blank">h=
ttps://lists.sourceforge.net/lists/listinfo/sbcl-commits</a><br></div></div=
>
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