Re: [Sbcl-commits] master: arm64-arch.c: Fix soft-simulation of some instructions.
Charles Zhang via Sbcl-devel <[email protected]> Thu, 21 May 2026 08:09:07 +0000 (UTC)
| Newsgroups | gmane.lisp.steel-bank.devel |
|---|---|
| Message-ID | <[email protected]> |
--===============7637259016926859625== Content-Type: multipart/alternative; boundary="----=_Part_4135904_1520911602.1779350947941" Content-Length: 26332 ------=_Part_4135904_1520911602.1779350947941 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Oh, right. Thanks for tracking these issues down. I look forward to any masochist=E2=80=99s=C2=A0x86-64 software=C2=A0impleme= ntation to make breakpoint tracing thread safe. :) On Thursday, May 21, 2026, 12:30 AM, Stas Boukarev <[email protected]> wro= te: It's a safepoint. On Thu, May 21, 2026 at 12:22=E2=80=AFAM Charles Zhang <charleszhang99@yaho= o.com> wrote: > > Thanks. Not a proper fix because I don't have a Windows machine. I'm thor= oughly confused about why this is Windows only. > > > > > > On Wednesday, May 20, 2026 at 08:29:14 PM GMT+2, Stas Boukarev <stassats@= gmail.com> wrote: > > > ::: Running (TRACE :ENCAPSULATE NIL) > fatal error encountered in SBCL pid 5521255184: > Unsupported LDR (literal) variant. > 0: 00000291caaa1938 pc=3D0000001000181ed0 {0000001000181dc0+0110} > SB-DI::BREAKPOINT-DO-DISPLACED-INST > 1: 00000291caaa1928 pc=3D00007ff7531059e0 > 2: 00000291caaa1900 pc=3D00000010019d75e0 {00000010019d7580+0060} > CL-USER::TRACE-THIS > > On Wed, May 20, 2026 at 1:14=E2=80=AFPM apache--- via Sbcl-commits > <[email protected]> wrote: > > > > The branch "master" has been updated in SBCL: > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 via=C2=A0 f982475b0bcb6d691cf172630fad9c1408= 7378b2 (commit) > >=C2=A0 =C2=A0 =C2=A0 from=C2=A0 07f82d35917900fe1222891579c2fe9d3d8df3c4= (commit) > > > > - Log ----------------------------------------------------------------- > > commit f982475b0bcb6d691cf172630fad9c14087378b2 > > Author: Charles Zhang <[email protected]> > > Date:=C2=A0 Tue Mar 17 15:18:20 2026 +0100 > > > >=C2=A0 =C2=A0 arm64-arch.c: Fix soft-simulation of some instructions. > > > >=C2=A0 =C2=A0 For breakpoint support. > > --- > >=C2=A0 src/runtime/arm64-arch.c | 63 ++++++++++++++++++++++++++++++-----= ------------- > >=C2=A0 1 file changed, 39 insertions(+), 24 deletions(-) > > > > diff --git a/src/runtime/arm64-arch.c b/src/runtime/arm64-arch.c > > index 9183013fe..e9e8d3af1 100644 > > --- a/src/runtime/arm64-arch.c > > +++ b/src/runtime/arm64-arch.c > > @@ -88,20 +88,35 @@ condition_holds(os_context_t *context, unsigned int= cond) > >=C2=A0 { > >=C2=A0 =C2=A0 =C2=A0 int flags =3D *os_context_flags_addr(context); > >=C2=A0 =C2=A0 =C2=A0 bool result; > > -=C2=A0 =C2=A0 // Evaluate base condition. > > -=C2=A0 =C2=A0 switch (cond) { > > -=C2=A0 =C2=A0 case 0b000: result =3D ((flags >> Z_BIT) & 1); > > -=C2=A0 =C2=A0 case 0b001: result =3D ((flags >> C_BIT) & 1); > > -=C2=A0 =C2=A0 case 0b010: result =3D ((flags >> N_BIT) & 1); > > -=C2=A0 =C2=A0 case 0b011: result =3D ((flags >> V_BIT) & 1); > > -=C2=A0 =C2=A0 case 0b100: result =3D ((flags >> V_BIT) & 1) && ~((flag= s >> Z_BIT) & 1); > > -=C2=A0 =C2=A0 case 0b101: result =3D ((flags >> N_BIT) =3D=3D (flags >= > V_BIT)); > > -=C2=A0 =C2=A0 case 0b110: result =3D ((flags >> N_BIT) =3D=3D (flags >= > V_BIT)) && !((flags >> Z_BIT) & 1); > > -=C2=A0 =C2=A0 case 0b111: result =3D 1; > > +=C2=A0 =C2=A0 // Evaluate base condition (ignoring the inversion bit). > > +=C2=A0 =C2=A0 switch (cond >> 1) { > > +=C2=A0 =C2=A0 case 0b000: > > +=C2=A0 =C2=A0 =C2=A0 result =3D (flags >> Z_BIT) & 1; > > +=C2=A0 =C2=A0 =C2=A0 break; > > +=C2=A0 =C2=A0 case 0b001: > > +=C2=A0 =C2=A0 =C2=A0 result =3D (flags >> C_BIT) & 1; > > +=C2=A0 =C2=A0 =C2=A0 break; > > +=C2=A0 =C2=A0 case 0b010: > > +=C2=A0 =C2=A0 =C2=A0 result =3D (flags >> N_BIT) & 1; > > +=C2=A0 =C2=A0 =C2=A0 break; > > +=C2=A0 =C2=A0 case 0b011: result =3D (flags >> V_BIT) & 1; > > +=C2=A0 =C2=A0 =C2=A0 break; > > +=C2=A0 =C2=A0 case 0b100: > > +=C2=A0 =C2=A0 =C2=A0 result =3D ((flags >> C_BIT) & 1) && !((flags >> = Z_BIT) & 1); > > +=C2=A0 =C2=A0 =C2=A0 break; > > +=C2=A0 =C2=A0 case 0b101: > > +=C2=A0 =C2=A0 =C2=A0 result =3D ((flags >> N_BIT) & 1) =3D=3D ((flags = >> V_BIT) & 1); > > +=C2=A0 =C2=A0 =C2=A0 break; > > +=C2=A0 =C2=A0 case 0b110: > > +=C2=A0 =C2=A0 =C2=A0 result =3D ((flags >> N_BIT) & 1) =3D=3D ((flags = >> V_BIT) & 1) && !((flags >> Z_BIT) & 1); > > +=C2=A0 =C2=A0 =C2=A0 break; > > +=C2=A0 =C2=A0 default: > > +=C2=A0 =C2=A0 =C2=A0 result =3D 1; > > +=C2=A0 =C2=A0 =C2=A0 break; > >=C2=A0 =C2=A0 =C2=A0 } > > > > -=C2=A0 =C2=A0 // Condition flag values in the set '111x' indicate alwa= ys true > > -=C2=A0 =C2=A0 // Otherwise, invert condition if necessary. > > +=C2=A0 =C2=A0 // Condition flag values in the set '111x' indicate alwa= ys true. > > +=C2=A0 =C2=A0 // Otherwise, invert condition if the low bit is set. > >=C2=A0 =C2=A0 =C2=A0 if ((cond & 0b1) && (cond !=3D 0b1111)) > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 result =3D !result; > > > > @@ -158,12 +173,10 @@ void arch_do_displaced_inst(os_context_t *context= , unsigned int orig_inst) > >=C2=A0 =C2=A0 =C2=A0 } > >=C2=A0 =C2=A0 =C2=A0 else if (((orig_inst >> 25) & 0b111111) =3D=3D 0b01= 1010) { > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 // Compare branch imm > > -=C2=A0 =C2=A0 =C2=A0 =C2=A0 bool size_is_64 =3D (orig_inst >> 31) & 0b= 1; > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bool op =3D (orig_inst >> 24) & 0b1; > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int offset =3D sign_extend((orig_inst= >> 5) & ~(1 << 19), 19); > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int rt =3D orig_inst & 0b11111; > > -=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!size_is_64) lose("Size must be 64 bit= s."); > > -=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (*os_context_register_addr(context, rt)= ^ op) > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if ((!*os_context_register_addr(context, r= t)) ^ op) > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 next_pc +=3D offset; > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 else > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 next_pc +=3D 1; > > @@ -173,32 +186,34 @@ void arch_do_displaced_inst(os_context_t *context= , unsigned int orig_inst) > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bool b5 =3D (orig_inst >> 31) & 0b1; > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bool op =3D (orig_inst >> 24) & 0b1; > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bool b40 =3D (orig_inst >> 19) & 0b11= 111; > > -=C2=A0 =C2=A0 =C2=A0 =C2=A0 int bit_pos =3D (b5 << 6) | b40; > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 int bit_pos =3D (b5 << 5) | b40; > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int offset =3D sign_extend((orig_inst= >> 5) & ~(1 << 14), 14); > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int rt =3D orig_inst & 0b11111; > > -=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!b5) lose("b5 must be 64 bits."); > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (((*os_context_register_addr(conte= xt, rt) >> bit_pos) & 0b1) ^ op) > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 next_pc +=3D offset; > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 else > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 next_pc +=3D 1; > >=C2=A0 =C2=A0 =C2=A0 } > > -=C2=A0 =C2=A0 else if (((orig_inst >> 31) & 0b1) =3D=3D 0b0) { > > +=C2=A0 =C2=A0 else if (((orig_inst >> 24) & 0b11111) =3D=3D 0b11000) { > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 // LDR (literal) > > -=C2=A0 =C2=A0 =C2=A0 =C2=A0 bool size_is_64 =3D (orig_inst >> 30) & 0b= 1; > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 int opc =3D (orig_inst >> 30) & 0b11; > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int rt =3D orig_inst & 0b11111; > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int offset =3D sign_extend((orig_inst= >> 5) & ~(1 << 19), 19); > > -=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!size_is_64) lose("Size must be 64 bit= s."); > > -=C2=A0 =C2=A0 =C2=A0 =C2=A0 *os_context_register_addr(context, rt) =3D= *((lispobj*)(pc + offset)); > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (opc =3D=3D 0b01) > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *os_context_register_addr(context, = rt) =3D *((uint64_t *)(pc + offset)); > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 else if (opc =3D=3D 0b00) > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *os_context_register_addr(context, = rt) =3D *((uint32_t *)(pc + offset)); > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 else > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 lose("Unsupported LDR (literal) var= iant."); > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 next_pc +=3D 1; > >=C2=A0 =C2=A0 =C2=A0 } > >=C2=A0 =C2=A0 =C2=A0 else if (((orig_inst >> 24) & 0b11111) =3D=3D 0b100= 00) { > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 // ADR(P) > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bool op =3D (orig_inst >> 31) & 0b1; > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int rd =3D orig_inst & 0b11111; > > -=C2=A0 =C2=A0 =C2=A0 =C2=A0 int imm =3D sign_extend(((orig_inst >> 5) = & ~(1 << 19)) | > > -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ((orig_inst >> 29) & ~(1 << 2)), 21); > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 int imm =3D sign_extend(((orig_inst >> 3) = & 0x1FFFFC) | ((orig_inst >> 29) & 3), 21); > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (op) // ADRP > > -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *os_context_register_addr(co= ntext, rd) =3D ((uword_t)pc & ~(1 << 12)) + (imm << 12); > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *os_context_register_addr(co= ntext, rd) =3D ((uword_t)pc & ~(uword_t)0xFFF) + ((sword_t)imm << 12); > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 else // ADR > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *os_context_register_ad= dr(context, rd) =3D (uword_t)pc + imm; > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 next_pc +=3D 1; > > > > ----------------------------------------------------------------------- > > > > > > hooks/post-receive > > -- > > SBCL > > > > > > _______________________________________________ > > Sbcl-commits mailing list > > [email protected] > > https://lists.sourceforge.net/lists/listinfo/sbcl-commits ------=_Part_4135904_1520911602.1779350947941 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable <html xmlns=3D"http://www.w3.org/1999/xhtml" xmlns:v=3D"urn:schemas-microso= ft-com:vml" xmlns:o=3D"urn:schemas-microsoft-com:office:office"><head><!--[= if gte mso 9]><xml><o:OfficeDocumentSettings><o:AllowPNG/><o:PixelsPerInch>= 96</o:PixelsPerInch></o:OfficeDocumentSettings></xml><![endif]--></head><bo= dy> Oh, right. Thanks for tracking these issues down.<br><br>I look forward to = any masochist=E2=80=99s x86-64 software implementation to make br= eakpoint tracing thread safe. :)<br><p class=3D"yahoo-quoted-begin" style= =3D"font-size: 15px; padding-top: 15px; margin-top: 0">On Thursday, May 21,= 2026, 12:30 AM, Stas Boukarev <<span style=3D"color: rgb(var(--links-ca= ret-color)) !important">[email protected]</span>> wrote:</p><blockquote= class=3D"iosymail"><div dir=3D"ltr">It's a safepoint.<br></div><div dir=3D= "ltr"><br></div><div dir=3D"ltr">On Thu, May 21, 2026 at 12:22=E2=80=AFAM C= harles Zhang <<a ymailto=3D"mailto:[email protected]" href=3D"mai= lto:[email protected]">[email protected]</a>> wrote:<br></= div><div dir=3D"ltr">><br></div><div dir=3D"ltr">> Thanks. Not a prop= er fix because I don't have a Windows machine. I'm thoroughly confused abou= t why this is Windows only.<br></div><div dir=3D"ltr">><br></div><div di= r=3D"ltr">><br></div><div dir=3D"ltr">><br></div><div dir=3D"ltr">>= ;<br></div><div dir=3D"ltr">><br></div><div dir=3D"ltr">> On Wednesda= y, May 20, 2026 at 08:29:14 PM GMT+2, Stas Boukarev <<a ymailto=3D"mailt= o:[email protected]" href=3D"mailto:[email protected]">[email protected]= </a>> wrote:<br></div><div dir=3D"ltr">><br></div><div dir=3D"ltr">&g= t;<br></div><div dir=3D"ltr">> ::: Running (TRACE :ENCAPSULATE NIL)<br><= /div><div dir=3D"ltr">> fatal error encountered in SBCL pid 5521255184:<= br></div><div dir=3D"ltr">> Unsupported LDR (literal) variant.<br></div>= <div dir=3D"ltr">> 0: 00000291caaa1938 pc=3D0000001000181ed0 {0000001000= 181dc0+0110}<br></div><div dir=3D"ltr">> SB-DI::BREAKPOINT-DO-DISPLACED-= INST<br></div><div dir=3D"ltr">> 1: 00000291caaa1928 pc=3D00007ff7531059= e0<br></div><div dir=3D"ltr">> 2: 00000291caaa1900 pc=3D00000010019d75e0= {00000010019d7580+0060}<br></div><div dir=3D"ltr">> CL-USER::TRACE-THIS= <br></div><div dir=3D"ltr">><br></div><div dir=3D"ltr">> On Wed, May = 20, 2026 at 1:14=E2=80=AFPM apache--- via Sbcl-commits<br></div><div dir=3D= "ltr">> <<a ymailto=3D"mailto:[email protected]" hre= f=3D"mailto:[email protected]">[email protected]= rge.net</a>> wrote:<br></div><div dir=3D"ltr">> ><br></div><div di= r=3D"ltr">> > The branch "master" has been updated in SBCL:<br></div>= <div dir=3D"ltr">> > via f982475b0bc= b6d691cf172630fad9c14087378b2 (commit)<br></div><div dir=3D"ltr">> >&= nbsp; from 07f82d35917900fe1222891579c2fe9d3d8df3c4 (co= mmit)<br></div><div dir=3D"ltr">> ><br></div><div dir=3D"ltr">> &g= t; - Log -----------------------------------------------------------------<= br></div><div dir=3D"ltr">> > commit f982475b0bcb6d691cf172630fad9c14= 087378b2<br></div><div dir=3D"ltr">> > Author: Charles Zhang <<a y= mailto=3D"mailto:[email protected]" href=3D"mailto:charleszhang99@ya= hoo.com">[email protected]</a>><br></div><div dir=3D"ltr">> &g= t; Date: Tue Mar 17 15:18:20 2026 +0100<br></div><div dir=3D"ltr">>= ; ><br></div><div dir=3D"ltr">> > arm64-arch.c: Fix s= oft-simulation of some instructions.<br></div><div dir=3D"ltr">> ><br= ></div><div dir=3D"ltr">> > For breakpoint support.<br><= /div><div dir=3D"ltr">> > ---<br></div><div dir=3D"ltr">> >&nbs= p; src/runtime/arm64-arch.c | 63 ++++++++++++++++++++++++++++++------------= ------<br></div><div dir=3D"ltr">> > 1 file changed, 39 inserti= ons(+), 24 deletions(-)<br></div><div dir=3D"ltr">> ><br></div><div d= ir=3D"ltr">> > diff --git a/src/runtime/arm64-arch.c b/src/runtime/ar= m64-arch.c<br></div><div dir=3D"ltr">> > index 9183013fe..e9e8d3af1 1= 00644<br></div><div dir=3D"ltr">> > --- a/src/runtime/arm64-arch.c<br= ></div><div dir=3D"ltr">> > +++ b/src/runtime/arm64-arch.c<br></div><= div dir=3D"ltr">> > @@ -88,20 +88,35 @@ condition_holds(os_context_t = *context, unsigned int cond)<br></div><div dir=3D"ltr">> > {<br= ></div><div dir=3D"ltr">> > int flags =3D *os_con= text_flags_addr(context);<br></div><div dir=3D"ltr">> > = bool result;<br></div><div dir=3D"ltr">> > - // E= valuate base condition.<br></div><div dir=3D"ltr">> > - = switch (cond) {<br></div><div dir=3D"ltr">> > - case 0b0= 00: result =3D ((flags >> Z_BIT) & 1);<br></div><div dir=3D"ltr">= > > - case 0b001: result =3D ((flags >> C_BIT) &am= p; 1);<br></div><div dir=3D"ltr">> > - case 0b010: resul= t =3D ((flags >> N_BIT) & 1);<br></div><div dir=3D"ltr">> >= - case 0b011: result =3D ((flags >> V_BIT) & 1);<br= ></div><div dir=3D"ltr">> > - case 0b100: result =3D ((f= lags >> V_BIT) & 1) && ~((flags >> Z_BIT) & 1);= <br></div><div dir=3D"ltr">> > - case 0b101: result =3D = ((flags >> N_BIT) =3D=3D (flags >> V_BIT));<br></div><div dir= =3D"ltr">> > - case 0b110: result =3D ((flags >> N= _BIT) =3D=3D (flags >> V_BIT)) && !((flags >> Z_BIT) &a= mp; 1);<br></div><div dir=3D"ltr">> > - case 0b111: resu= lt =3D 1;<br></div><div dir=3D"ltr">> > + // Evaluate ba= se condition (ignoring the inversion bit).<br></div><div dir=3D"ltr">> &= gt; + switch (cond >> 1) {<br></div><div dir=3D"ltr">>= ; > + case 0b000:<br></div><div dir=3D"ltr">> > +&nbs= p; result =3D (flags >> Z_BIT) & 1;<br></div><div d= ir=3D"ltr">> > + break;<br></div><div dir=3D"ltr"= >> > + case 0b001:<br></div><div dir=3D"ltr">> > += result =3D (flags >> C_BIT) & 1;<br></div><d= iv dir=3D"ltr">> > + break;<br></div><div dir=3D"= ltr">> > + case 0b010:<br></div><div dir=3D"ltr">> &g= t; + result =3D (flags >> N_BIT) & 1;<br></di= v><div dir=3D"ltr">> > + break;<br></div><div dir= =3D"ltr">> > + case 0b011: result =3D (flags >> V_= BIT) & 1;<br></div><div dir=3D"ltr">> > + bre= ak;<br></div><div dir=3D"ltr">> > + case 0b100:<br></div= ><div dir=3D"ltr">> > + result =3D ((flags >&g= t; C_BIT) & 1) && !((flags >> Z_BIT) & 1);<br></div><= div dir=3D"ltr">> > + break;<br></div><div dir=3D= "ltr">> > + case 0b101:<br></div><div dir=3D"ltr">> &= gt; + result =3D ((flags >> N_BIT) & 1) =3D= =3D ((flags >> V_BIT) & 1);<br></div><div dir=3D"ltr">> > += break;<br></div><div dir=3D"ltr">> > + &nb= sp; case 0b110:<br></div><div dir=3D"ltr">> > + r= esult =3D ((flags >> N_BIT) & 1) =3D=3D ((flags >> V_BIT) &= amp; 1) && !((flags >> Z_BIT) & 1);<br></div><div dir=3D"= ltr">> > + break;<br></div><div dir=3D"ltr">> = > + default:<br></div><div dir=3D"ltr">> > + &n= bsp; result =3D 1;<br></div><div dir=3D"ltr">> > +  = ; break;<br></div><div dir=3D"ltr">> > }<b= r></div><div dir=3D"ltr">> ><br></div><div dir=3D"ltr">> > -&nb= sp; // Condition flag values in the set '111x' indicate always true<= br></div><div dir=3D"ltr">> > - // Otherwise, invert con= dition if necessary.<br></div><div dir=3D"ltr">> > + // = Condition flag values in the set '111x' indicate always true.<br></div><div= dir=3D"ltr">> > + // Otherwise, invert condition if the= low bit is set.<br></div><div dir=3D"ltr">> > if= ((cond & 0b1) && (cond !=3D 0b1111))<br></div><div dir=3D"ltr"= >> > result =3D !result;<br></div><= div dir=3D"ltr">> ><br></div><div dir=3D"ltr">> > @@ -158,12 +1= 73,10 @@ void arch_do_displaced_inst(os_context_t *context, unsigned int or= ig_inst)<br></div><div dir=3D"ltr">> > }<br></div= ><div dir=3D"ltr">> > else if (((orig_inst >&g= t; 25) & 0b111111) =3D=3D 0b011010) {<br></div><div dir=3D"ltr">> &g= t; // Compare branch imm<br></div><div di= r=3D"ltr">> > - bool size_is_64 =3D (orig_= inst >> 31) & 0b1;<br></div><div dir=3D"ltr">> > &nbs= p; bool op =3D (orig_inst >> 24) & 0b1;<br><= /div><div dir=3D"ltr">> > int offse= t =3D sign_extend((orig_inst >> 5) & ~(1 << 19), 19);<br></= div><div dir=3D"ltr">> > int rt =3D= orig_inst & 0b11111;<br></div><div dir=3D"ltr">> > -  = ; if (!size_is_64) lose("Size must be 64 bits.");<br></div><d= iv dir=3D"ltr">> > - if (*os_context_regis= ter_addr(context, rt) ^ op)<br></div><div dir=3D"ltr">> > + &nb= sp; if ((!*os_context_register_addr(context, rt)) ^ op)<br></= div><div dir=3D"ltr">> > &nb= sp; next_pc +=3D offset;<br></div><div dir=3D"ltr">> > &= nbsp; else<br></div><div dir=3D"ltr">> > &= nbsp; next_pc +=3D 1;<br></div><div dir=3D"ltr"= >> > @@ -173,32 +186,34 @@ void arch_do_displaced_inst(os_context_t *= context, unsigned int orig_inst)<br></div><div dir=3D"ltr">> > = bool b5 =3D (orig_inst >> 31) & 0b1;<= br></div><div dir=3D"ltr">> > bool = op =3D (orig_inst >> 24) & 0b1;<br></div><div dir=3D"ltr">> &g= t; bool b40 =3D (orig_inst >> 19) &= amp; 0b11111;<br></div><div dir=3D"ltr">> > - &nb= sp; int bit_pos =3D (b5 << 6) | b40;<br></div><div dir=3D"ltr">> &= gt; + int bit_pos =3D (b5 << 5) | b40;<br>= </div><div dir=3D"ltr">> > int offs= et =3D sign_extend((orig_inst >> 5) & ~(1 << 14), 14);<br><= /div><div dir=3D"ltr">> > int rt = =3D orig_inst & 0b11111;<br></div><div dir=3D"ltr">> > - &n= bsp; if (!b5) lose("b5 must be 64 bits.");<br></div><div dir= =3D"ltr">> > if (((*os_context_regi= ster_addr(context, rt) >> bit_pos) & 0b1) ^ op)<br></div><div dir= =3D"ltr">> > next_pc = +=3D offset;<br></div><div dir=3D"ltr">> > = else<br></div><div dir=3D"ltr">> > = next_pc +=3D 1;<br></div><div dir=3D"ltr">> >&n= bsp; }<br></div><div dir=3D"ltr">> > - els= e if (((orig_inst >> 31) & 0b1) =3D=3D 0b0) {<br></div><div dir= =3D"ltr">> > + else if (((orig_inst >> 24) & 0= b11111) =3D=3D 0b11000) {<br></div><div dir=3D"ltr">> > = // LDR (literal)<br></div><div dir=3D"ltr">> > -= bool size_is_64 =3D (orig_inst >> 30) &am= p; 0b1;<br></div><div dir=3D"ltr">> > + in= t opc =3D (orig_inst >> 30) & 0b11;<br></div><div dir=3D"ltr">>= ; > int rt =3D orig_inst & 0b11111= ;<br></div><div dir=3D"ltr">> > int= offset =3D sign_extend((orig_inst >> 5) & ~(1 << 19), 19);= <br></div><div dir=3D"ltr">> > - if (!size= _is_64) lose("Size must be 64 bits.");<br></div><div dir=3D"ltr">> > = - *os_context_register_addr(context, rt) =3D *((= lispobj*)(pc + offset));<br></div><div dir=3D"ltr">> > + = if (opc =3D=3D 0b01)<br></div><div dir=3D"ltr">> > +&n= bsp; *os_context_register_addr(context, rt) =3D= *((uint64_t *)(pc + offset));<br></div><div dir=3D"ltr">> > + = else if (opc =3D=3D 0b00)<br></div><div dir=3D"ltr">&g= t; > + *os_context_register_addr(conte= xt, rt) =3D *((uint32_t *)(pc + offset));<br></div><div dir=3D"ltr">> &g= t; + else<br></div><div dir=3D"ltr">> > +&= nbsp; lose("Unsupported LDR (literal) variant."= );<br></div><div dir=3D"ltr">> > ne= xt_pc +=3D 1;<br></div><div dir=3D"ltr">> > }<br>= </div><div dir=3D"ltr">> > else if (((orig_inst &= gt;> 24) & 0b11111) =3D=3D 0b10000) {<br></div><div dir=3D"ltr">>= > // ADR(P)<br></div><div dir=3D"ltr"= >> > bool op =3D (orig_inst >>= ; 31) & 0b1;<br></div><div dir=3D"ltr">> > &n= bsp; int rd =3D orig_inst & 0b11111;<br></div><div dir=3D"ltr">&= gt; > - int imm =3D sign_extend(((orig_inst &= gt;> 5) & ~(1 << 19)) |<br></div><div dir=3D"ltr">> > -&= nbsp; = ((orig_inst >> 29) & ~(1 << 2)= ), 21);<br></div><div dir=3D"ltr">> > + in= t imm =3D sign_extend(((orig_inst >> 3) & 0x1FFFFC) | ((orig_inst= >> 29) & 3), 21);<br></div><div dir=3D"ltr">> > &nbs= p; if (op) // ADRP<br></div><div dir=3D"ltr">> >= - *os_context_register_addr(conte= xt, rd) =3D ((uword_t)pc & ~(1 << 12)) + (imm << 12);<br></= div><div dir=3D"ltr">> > + *= os_context_register_addr(context, rd) =3D ((uword_t)pc & ~(uword_t)0xFF= F) + ((sword_t)imm << 12);<br></div><div dir=3D"ltr">> > = else // ADR<br></div><div dir=3D"ltr">> >= *os_context_register_addr(= context, rd) =3D (uword_t)pc + imm;<br></div><div dir=3D"ltr">> >&nbs= p; next_pc +=3D 1;<br></div><div dir=3D"ltr">&g= t; ><br></div><div dir=3D"ltr">> > -------------------------------= ----------------------------------------<br></div><div dir=3D"ltr">> >= ;<br></div><div dir=3D"ltr">> ><br></div><div dir=3D"ltr">> > h= ooks/post-receive<br></div><div dir=3D"ltr">> > --<br></div><div dir= =3D"ltr">> > SBCL<br></div><div dir=3D"ltr">> ><br></div><div d= ir=3D"ltr">> ><br></div><div dir=3D"ltr">> > __________________= _____________________________<br></div><div dir=3D"ltr">> > Sbcl-comm= its mailing list<br></div><div dir=3D"ltr">> > <a ymailto=3D"mailto:S= [email protected]" href=3D"mailto:[email protected]= forge.net">[email protected]</a><br></div><div dir=3D"ltr"= >> > <a href=3D"https://lists.sourceforge.net/lists/listinfo/sbcl-com= mits" target=3D"_blank">https://lists.sourceforge.net/lists/listinfo/sbcl-c= ommits</a><br></div><blockquote></blockquote></blockquote> </body></html> ------=_Part_4135904_1520911602.1779350947941-- --===============7637259016926859625== Content-Type: text/plain; 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