Re: [PATCH] [pciextra] Restore the PCI COMMAND register after writing to the BARs
Shao Miller <[email protected]> Sun, 29 Nov 2009 16:29:44 -0500
| Newsgroups | gmane.network.etherboot.gpxe,gmane.network.etherboot.devel |
|---|---|
| Message-ID | <[email protected]> |
This is a multi-part MIME message. --===============0576867634== Content-Type: multipart/alternative; boundary="=_reb-r152065F0-t4B12E796" This is a multi-part MIME message. --=_reb-r152065F0-t4B12E796 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Bernhard Kohl wrote: > > Hi, > > This seems to be necessary for some types of PCI devices. We got problems > when using gPXE in KVM virtual machines with direct PCI device access. > > The PCI spec says: > Decode (I/O or memory) of a register is disabled via the command > register before > sizing a Base Address register. Software saves the original value of the > Base > Address register, writes 0FFFFFFFFh to the register, then reads it back. > ... > The original value in the Base Address register is restored before > reenabling > decode in the command register of the device. > Thanks, Bernhard. This has been noted at http://support.etherboot.org/index.php?do=details&task_id=40 - Shao Miller --=_reb-r152065F0-t4B12E796 Content-Type: text/html; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mail.yrbe.edu.on.ca id nATLOac8030834 <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"> <html> <head> =20 </head> <body text=3D"#000000" bgcolor=3D"#ffffff"> Bernhard Kohl wrote: <blockquote type=3D"cite" cite=3D"mid:[email protected]"> =20 =20 <title>[Etherboot-developers] [PATCH] [pciextra] Restore the PCI COMMAND register after writing to the BARs</title> <!-- Converted from text/plain format --> <p><font size=3D"2">Hi,<br> <br> This seems to be necessary for some types of PCI devices. We got problems<br> when using gPXE in KVM virtual machines with direct PCI device access.<br> <br> The PCI spec says:<br> Decode (I/O or memory) of a register is disabled via the command<br> register before<br> sizing a Base Address register. Software saves the original value of the<br> Base<br> Address register, writes 0FFFFFFFFh to the register, then reads it back.<br> ...<br> The original value in the Base Address register is restored before<br> reenabling<br> decode in the command register of the device.</font></p> </blockquote> Thanks, Bernhard.=A0 This has been noted at <a href=3D"http://support.etherboot.org/index.php?do=3Ddetails&task_id=3D40= " class=3D"moz-txt-link-freetext">http://support.etherboot.org/index.php?do= =3Ddetails&task_id=3D40</a><br> <br> - Shao Miller<br> </body> </html> --=_reb-r152065F0-t4B12E796-- --===============0576867634== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ gPXE mailing list [email protected] http://etherboot.org/mailman/listinfo/gpxe --===============0576867634==--