Re: [PATCH] [pciextra] Restore the PCI COMMAND register after writing to the BARs
Shao Miller <[email protected]> Wed, 20 Jan 2010 23:22:00 -0500
| Newsgroups | gmane.network.etherboot.gpxe,gmane.network.etherboot.devel |
|---|---|
| Message-ID | <[email protected]> |
This is a multi-part MIME message. --=_reb-r6D4542CF-t4B57D66B Content-Type: multipart/alternative; boundary="=_reb-r7B5262BE-t4B57D66B" This is a multi-part MIME message. --=_reb-r7B5262BE-t4B57D66B Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit I wrote: > Bernhard Kohl wrote: >> >> Hi, >> >> This seems to be necessary for some types of PCI devices. We got problems >> when using gPXE in KVM virtual machines with direct PCI device access. >> >> The PCI spec says: >> Decode (I/O or memory) of a register is disabled via the command >> register before >> sizing a Base Address register. Software saves the original value of the >> Base >> Address register, writes 0FFFFFFFFh to the register, then reads it back. >> ... >> The original value in the Base Address register is restored before >> reenabling >> decode in the command register of the device. >> > Thanks, Bernhard. This has been noted at > http://support.etherboot.org/index.php?do=details&task_id=40 Bernhard, I notice that we might actually wish to disable memory space access... I've made a modified patch, attached. Could you please test it out? Also available at: http://git.etherboot.org/?p=people/sha0/gpxe.git;a=commitdiff;h=86761eafd7451b084ca67c3b10852e50a85f9ee1 Thanks again! - Shao Miller --=_reb-r7B5262BE-t4B57D66B Content-Type: text/html; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mail.yrbe.edu.on.ca id o0L4CsQi016811 <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"> <html> <head> =20 <title></title> </head> <body text=3D"#000000" bgcolor=3D"#ffffff"> <tt>I wrote:</tt> <blockquote type=3D"cite" cite=3D"mid:[email protected]"><tt> Bernhard Kohl wrote: </tt> <blockquote type=3D"cite" cite=3D"mid:[email protected]"> =20 =20 <title>[Etherboot-developers] [PATCH] [pciextra] Restore the PCI COMMAND register after writing to the BARs</title> <!-- Converted from text/plain format --> <p><tt><font size=3D"2">Hi,<br> <br> This seems to be necessary for some types of PCI devices. We got problems<br> when using gPXE in KVM virtual machines with direct PCI device access.<br> <br> The PCI spec says:<br> Decode (I/O or memory) of a register is disabled via the command<br> register before<br> sizing a Base Address register. Software saves the original value of the<br> Base<br> Address register, writes 0FFFFFFFFh to the register, then reads it back.<br> ...<br> The original value in the Base Address register is restored before<br> reenabling<br> decode in the command register of the device.</font></tt></p> </blockquote> <tt>Thanks, Bernhard.=A0 This has been noted at <a href=3D"http://support.etherboot.org/index.php?do=3Ddetails&task_i= d=3D40" class=3D"moz-txt-link-freetext" moz-do-not-send=3D"true">http://sup= port.etherboot.org/index.php?do=3Ddetails&task_id=3D40</a></tt></blockq= uote> <tt><br> Bernhard, I notice that we might actually wish to disable memory space access...=A0 I've made a modified patch, attached.=A0 Could you please test it out?=A0 Also available at: <a href=3D"http://git.etherboot.org/?p=3Dpeople/sha0/gpxe.git;a=3Dcommitdif= f;h=3D86761eafd7451b084ca67c3b10852e50a85f9ee1" class=3D"moz-txt-link-freet= ext">http://git.etherboot.org/?p=3Dpeople/sha0/gpxe.git;a=3Dcommitdiff;h=3D= 86761eafd7451b084ca67c3b10852e50a85f9ee1</a><br> <br> Thanks again!<br> <br> - Shao Miller<br> </tt> </body> </html> --=_reb-r7B5262BE-t4B57D66B-- --=_reb-r6D4542CF-t4B57D66B Content-Type: text/plain; name="0001-pci-Disable-memory-access-restore-BAR-and-comman.patch" Content-Disposition: inline; filename*0="0001-pci-Disable-memory-access-restore-BAR-and-comman.patch" Content-Transfer-Encoding: quoted-printable =46rom 86761eafd7451b084ca67c3b10852e50a85f9ee1 Mon Sep 17 00:00:00 2001 From: Bernhard Kohl <[email protected]> Date: Wed, 20 Jan 2010 23:06:39 -0500 Subject: [PATCH] [pci] Disable memory access & restore BAR and command regi= ster This seems to be necessary for some types of PCI devices. We got problems when using gPXE in KVM virtual machines with direct PCI device access. The PCI spec says: Decode (I/O or memory) of a register is disabled via the command register before sizing a Base Address register. Software saves the original value of the Base Address register, writes 0FFFFFFFFh to the register, then reads it back. ... The original value in the Base Address register is restored before reenabling decode in the command register of the device. Signed-off-by: Bernhard Kohl <[email protected]> Modified-by: Shao Miller <[email protected]> Signed-off-by: Shao Miller <[email protected]> --- src/drivers/bus/pciextra.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/src/drivers/bus/pciextra.c b/src/drivers/bus/pciextra.c index 1dd63ee..ecc7232 100644 --- a/src/drivers/bus/pciextra.c +++ b/src/drivers/bus/pciextra.c @@ -60,15 +60,22 @@ int pci_find_capability ( struct pci_device *pci, int c= ap ) { * function. */ unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg ) { + uint16_t cmd; uint32_t start, size; =20 + /* Save the original command register */ + pci_read_config_word ( pci, PCI_COMMAND, &cmd ); /* Save the original bar */ pci_read_config_dword ( pci, reg, &start ); + /* Disable memory space access */ + pci_write_config_word ( pci, PCI_COMMAND, cmd & ~PCI_COMMAND_MEM ); /* Compute which bits can be set */ pci_write_config_dword ( pci, reg, ~0 ); pci_read_config_dword ( pci, reg, &size ); /* Restore the original size */ pci_write_config_dword ( pci, reg, start ); + /* Restore the original command register. This reenables decoding. */ + pci_write_config_word ( pci, PCI_COMMAND, cmd ); /* Find the significant bits */ if ( start & PCI_BASE_ADDRESS_SPACE_IO ) { size &=3D PCI_BASE_ADDRESS_IO_MASK; --=20 1.5.3.4 --=_reb-r6D4542CF-t4B57D66B Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ gPXE mailing list [email protected] http://etherboot.org/mailman/listinfo/gpxe --=_reb-r6D4542CF-t4B57D66B--