[Myrinet] [Q] two questions about Myrinet

Hello. I'm developing my own MCP on M2L-PCI64B NIC. 
I had been stucked to some strange problems and finally resolved my bugs(?).
Anyway, I have two questions about what I've experienced. 

1. When I am waiting for a DMA completion polling on the 'next' field of 
   DMA_BLOCK structure, I found that a special case DMA does not finish
   forever. The case was a single DMA block of which the 'next' field 
   pointing to itself. 

	example: 
		DMA_BLOCK dma_block;

		blur blur blur (1)
		dma_block->next = (&dma_block | direction | DMA_WAKE);
		while(!((dma_block->next) & DMA_TERMINAL));
		blur blur blur (2)

	In the above simple code, I can't reach line number (2) some times.

2. When I send a packet to a link, I got a similar situation. If I 
   set the 'SML' register and wait for a SEND_INT bit, I got a dirty 
   packet which was sent from a remote node. I set the timeout register
   as large as possible (i.e. TIMEOUT0 | TIMOUT1). But my MCP displays
   different packet contents from that of the packet sent. 

	example:

		blur blur blur
		send_packet();	// send a packet to a remote node
		while(!(ISR & SEND_INT_BIT));
		blur blur blur

		while(!(ISR & RECV_INT_BIT));
		recv_packet();	// receive a packet from a remote node	
		// I got a packet which shows dirty back-ends.

	The above situation is not deterministic. So I guess there may be race 
	condition. I don't know what is going on exactly.  Could anybody explain		why I got such phenomena?

Thank you for reading..


with regards,
sang



------------Korea Advanced Institute of Science and Technology-------------
Moon-Sang Lee	    [email protected]
CS dept. KAIST      +82-42-869-5585@calab  
Sarang Kwan. 524    +82-42-879-4145@dormitory
Homepage URL        http://camars.kaist.ac.kr/~mslee
---------------------Computer Architecture Laboratory----------------------