RE: sorry
"Zellal B" <[email protected]> Tue, 20 Jan 2004 07:13:36 +0000
| Newsgroups | gmane.org.handasarabia.general |
|---|---|
| Message-ID | <[email protected]> |
<html><div style='background-color:'><DIV class=RTE>
<P>am very sorry i have send u the wrong program.....this is the whole program and i wanted to divide it into 3 modules....i wish if u can guide me</P>
<P>-------------------------------------------------------------------------------<BR></P>
<P>library IEEE;<BR>use IEEE.std_logic_1164.all;<BR>use IEEE.std_logic_unsigned.all;<BR>use work.global_constants.all;</P>
<P>entity internet is<BR> port (<BR> clk: in STD_LOGIC; -- clock<BR> rstn: in STD_LOGIC; -- asynchronouse active low reset<BR> complete: in STD_LOGIC; -- control signal from ram arbitrator<BR> newFrame: in STD_LOGIC; -- new frame received from the layer below<BR> frameType: in STD_LOGIC; -- frame type = '1' for IP<BR> newFrameByte: in STD_LOGIC; -- signals a new byte in the stream<BR> frameData: in STD_LOGIC_VECTOR (7 downto 0); -- data is streamed in here<BR> endFrame: in STD_LOGIC; -- signals th
e end of a frame<BR> frameValid: in STD_LOGIC; -- determines validity of frame when endFrame is high<BR> newDatagram: out STD_LOGIC; -- an IP datagram has been fully received<BR> bufferSelect: out STD_LOGIC; -- indicates location of data in RAM, '0' = 10000, '1' = 20000<BR> datagramSize: out STD_LOGIC_VECTOR (15 downto 0); -- size of the datagram received<BR> protocol: out STD_LOGIC_VECTOR (7 downto 0); -- protocol type of datagram<BR> sourceIP: out STD_LOGIC_VECTOR (31 downto 0); -- lets upper protocol know the source IP<BR> wrRAM: out STD_LOGIC; -- signal to write to the RAM<BR> wrData: out STD_LOGIC_VECTOR (7 downto 0); &
nbsp; -- data to write to the RAM<BR> wrAddr: out STD_LOGIC_VECTOR (18 downto 0); -- address lines to the RAM for writing<BR> timeLED0: out STD_LOGIC; -- indicates if buffer 0 is busy<BR> timeLED1: out STD_LOGIC -- indicates if buffer 1 is busy<BR> );<BR>end internet;</P>
<P>architecture internet_arch of internet is</P>
<P>-- signal declarations<BR>-- FSM states<BR>type STATETYPE is (stIdle, stGetHeaderLen, stGetHeaderByte, stStoreHeaderByte, <BR> stGetDataByte, stSetupWriteDataByte, stCompleteFragment, stDoWrite, stgetNewByte);<BR>signal presState: STATETYPE;<BR>signal nextState: STATETYPE;<BR>signal returnState: STATETYPE; -- Used to return from RAM 'subroutines' </P>
<P>signal headerLen: STD_LOGIC_VECTOR (5 downto 0); -- IP datagram header length<BR>signal nextHeaderLen: STD_LOGIC_VECTOR (5 downto 0); -- signal for the next header lengh<BR>signal datagramLen: STD_LOGIC_VECTOR (10 downto 0); -- IP datagram total length in bytes<BR>signal nextDatagramLen: STD_LOGIC_VECTOR (10 downto 0); -- signal for the next datagram length<BR>signal dataLen: STD_LOGIC_VECTOR (10 downto 0); -- IP datagram data length in bytes<BR>signal nextDataLen: STD_LOGIC_VECTOR (10 downto 0); -- signal for the next data length</P>
<P>signal incCnt: STD_LOGIC; -- increments byte address counter<BR>signal rstCnt: STD_LOGIC; -- resets byte address counter<BR>signal cnt: STD_LOGIC_VECTOR (10 downto 0); -- byte address counter for the frame received</P>
<P>signal incWrCnt: STD_LOGIC; -- increments the write address counter<BR>signal rstWrCnt: STD_LOGIC; -- resets the write address counter<BR>signal wrCnt: STD_LOGIC_VECTOR (15 downto 0); -- write address counter for storing that data</P>
<P>signal doWrite: STD_LOGIC; -- tell RAM controller to write data<BR>signal getNewByte: STD_LOGIC; -- wait for new data on the stream</P>
<P>signal latchFrameData: STD_LOGIC; -- latch in the data from the stream<BR>signal frameDataLatch: STD_LOGIC_VECTOR (7 downto 0); -- register to hold latched data</P>
<P>signal targetIP: STD_LOGIC_VECTOR (31 downto 0); -- stores target IP (destination)<BR>signal shiftInTargetIP: STD_LOGIC; -- signal to shift in target IP</P>
<P>signal shiftInSourceIP: STD_LOGIC; -- stores source IP<BR>signal latchProtocol: STD_LOGIC; -- signal to shift in source IP</P>
<P>-- checksum signals<BR>signal checkState : STD_LOGIC;<BR>CONSTANT stMSB : STD_LOGIC := '0';<BR>CONSTANT stLSB : STD_LOGIC := '1';</P>
<P>signal checksumLong : STD_LOGIC_VECTOR (16 downto 0); -- stores 2's complement sum<BR>signal checksumInt : STD_LOGIC_VECTOR (15 downto 0); -- stores 1's complement sum</P>
<P>signal latchMSB : STD_LOGIC_VECTOR (7 downto 0); -- latch in first byte</P>
<P><BR>signal newHeader: STD_LOGIC; -- resets checksum<BR>signal newByte: STD_LOGIC; -- indicate new byte<BR>signal lastNewByte : STD_LOGIC; -- detect changes in newByte</P>
<P>signal inByte: STD_LOGIC_VECTOR (7 downto 0); -- byte to calculate</P>
<P>signal checksum: STD_LOGIC_VECTOR (15 downto 0); -- current checksum</P>
<P>-- bufferSelect is used both to indicate which area in RAM to write to<BR>-- and to indicate which buffer control ssignals are to operate on<BR>signal nextBufferSelect: STD_LOGIC; -- allows memory of bufferSelect<BR>signal bufferSelectSig : STD_LOGIC; -- allows memory of bufferSelect</P>
<P>signal identification: STD_LOGIC_VECTOR (15 downto 0); -- identification field<BR>signal shiftInIdentification: STD_LOGIC; -- signal to shift in identification</P>
<P>signal fragmentOffset: STD_LOGIC_VECTOR (12 downto 0); -- fragment offset field<BR>signal shiftInFragmentOffset: STD_LOGIC; -- signal to shift in offset<BR>signal moreFragments : STD_LOGIC; -- more fragments flag<BR>signal latchMoreFragments : STD_LOGIC; -- signal to determine MF flag</P>
<P>-- The ident signals are of the form "souurce IP : protocol : identification" and<BR>-- are used in reassembly.<BR>signal targetIdent: STD_LOGIC_VECTOR (55 downto 0); -- incoming frame's ident<BR>signal ident0: STD_LOGIC_VECTOR (55 downto 0); -- current ident for buffer 0<BR>signal ident1: STD_LOGIC_VECTOR (55 downto 0); -- current ident for buffer 1<BR>signal latchIdent: STD_LOGIC; -- latch targetIdent into specified buffer ident<BR>signal resetIdent: STD_LOGIC; -- clear ident of specified buffer to indicate a vacant buffer</P>
<P>signal position0: STD_LOGIC_VECTOR (15 downto 0); -- stores expected offset of next fragment<BR>signal position1: STD_LOGIC_VECTOR (15 downto 0); -- stores expected offset of next fragment<BR>signal updatePosition: STD_LOGIC; -- add dataLen to current position<BR>signal resetPosition: STD_LOGIC; -- set position to be dataLen</P>
<P>constant TIMERWIDTH : INTEGER := 30; -- can be used to vary timeout length</P>
<P>signal timeout0: STD_LOGIC_VECTOR (TIMERWIDTH - 1 downto 0); -- timeout counter<BR>signal timeout1: STD_LOGIC_VECTOR (TIMERWIDTH - 1 downto 0); -- timeout counter<BR>signal resetTimeout: STD_LOGIC; -- start timeout counter</P>
<P>constant FULLTIME: STD_LOGIC_VECTOR (TIMERWIDTH - 1 downto 0) := (others => '1'); -- last value of timeout counter</P>
<P>signal sourceIPSig : STD_LOGIC_VECTOR (31 downto 0); -- internal signal for output<BR>signal protocolSig : STD_LOGIC_VECTOR (7 downto 0); -- internal signal for output </P>
<P>begin<BR> -- These signals are used instead of buffer ports<BR> sourceIP <= sourceIPSig;<BR> protocol <= protocolSig;<BR> bufferSelect <= bufferSelectSig;<BR> <BR> -- Indicate when buffers are busy<BR> timeLED0 <= '0' when timeout0 = FULLTIME or ident0 = 0 else '1';<BR> timeLED1 <= '0' when timeout1 = FULLTIME or ident1 = 0 else '1';<BR> <BR> -- Some definitions to make further code simpler<BR> targetIdent <= sourceIPSig & protocolSig & identification;<BR> dataLen <= datagramLen - ("00000" & headerLen);<BR> <BR> -- main clocked process<BR> process (rstn, clk)<BR> begin<BR> if rstn = '0' then -- only need to reset required signals<BR> presState <= stIdle;<BR> returnState <= stIdle;<BR> ident0 <= (ot
hers => '0');<BR> ident1 <= (others => '0');<BR> timeout0 <= FULLTIME;<BR> timeout1 <= FULLTIME;</P>
<P> elsif clk'event and clk = '1' then</P>
<P> -- Go to next state wither directly or via a RAM state.<BR> -- If a RAM write or a new byte from the data stream are requested,<BR> -- the state machine stores nextState in returnState and goes to the<BR> -- required state. After completion, the state machine will go to <BR> -- returnState. This is like a 'subroutine' in the state machine.<BR> if doWrite = '1' then <BR> presState <= stDoWrite;<BR> returnState <= nextState;<BR> elsif getNewByte = '1' then<BR> presState <= stGetNewByte;<BR> returnState <= nextState;<BR> else<BR> presState <= nextState;<BR> end if;<BR> <BR>&n
bsp; -- increment and reset the counter synchronously to avoid race conditions<BR> if incCnt = '1' then<BR> cnt <= cnt + 1;<BR> elsif rstCnt = '1' then<BR> cnt <= (others => '0');<BR> end if;<BR> <BR> -- increment and reset the write address counter synchronously<BR> if incWrCnt = '1' then<BR> wrCnt <= wrCnt + 1;<BR> elsif rstWrCnt = '1' then<BR> wrCnt <= (others => '0');<BR> end if;<BR> <BR> -- latch data read from RAM<BR> if latchFrameData = '1' then<BR> frameDataLatch <= frameData;<BR> end if;<BR> <BR> --
these signals must remember their values once set<BR> headerLen <= nextHeaderLen;<BR> datagramLen <= nextDatagramLen;</P>
<P> -- shift registers and latches to hold important data<BR> if shiftInSourceIP = '1' then<BR> sourceIPSig <= sourceIPSig(23 downto 0) & frameDataLatch;<BR> end if;</P>
<P> if shiftInTargetIP = '1' then<BR> TargetIP <= TargetIP(23 downto 0) & frameDataLatch;<BR> end if;</P>
<P> if latchProtocol = '1' then<BR> protocolSig <= frameDataLatch;<BR> end if; </P>
<P> if shiftInFragmentOffset = '1' then<BR> fragmentOffset <= fragmentOffset (4 downto 0) & frameDataLatch;<BR> end if;</P>
<P> if latchMoreFragments = '1' then<BR> moreFragments <= frameDataLatch(5);<BR> end if;</P>
<P> if shiftInIdentification = '1' then<BR> identification <= identification (7 downto 0) & frameDataLatch;<BR> end if;<BR> <BR> -- bufferSelect will remember its previous value<BR> bufferSelectSig <= nextBufferSelect;<BR> <BR> -- handle timeout counters, resetTimeout will only reset the current buffer<BR> if resetTimeout = '1' then<BR> if bufferSelectSig = '0' then<BR> timeout0 <= (others => '0');<BR> else<BR> timeout1 <= (others => '0');<BR> end if;<BR> else<BR> -- increment timeout counters but don't let them overflow<BR> &nbs
p;if timeout0 /= FULLTIME then<BR> timeout0 <= timeout0 + 1;<BR> else<BR> timeout0 <= FULLTIME;<BR> end if;<BR> if timeout1 /= FULLTIME then<BR> timeout1 <= timeout1 + 1;<BR> else<BR> timeout1 <= FULLTIME;<BR> end if;<BR> end if;<BR> <BR> -- the following signals will operate only on the current buffer which<BR> -- is chosen with bufferSelect.<BR> if bufferSelectSig = '0' then<BR> -- manage the ident register of the buffer<BR> if latchIdent = '1' then<BR> ident0 <= targetIdent; <BR>
elsif resetIdent = '1' then<BR> ident0 <= (others => '0');<BR> end if;</P>
<P> -- manage the position register of the buffer<BR> if resetPosition = '1' then<BR> position0 <= "00000" & dataLen;<BR> elsif updatePosition = '1' then<BR> position0 <= position0 + dataLen;<BR> end if;</P>
<P> else <BR> -- manage the ident register of the buffer<BR> if latchIdent = '1' then<BR> ident1 <= targetIdent;<BR> elsif resetIdent = '1' then<BR> ident1 <= (others => '0');<BR> end if;<BR> <BR> -- manage the position register of the buffer <BR> if resetPosition = '1' then<BR> position1 <= "00000" & dataLen;<BR> elsif updatePosition = '1' then<BR> position1 <= position1 + dataLen;<BR> end if; <BR> end if;<BR> end if;<BR> end process;</P>
<P>-- IP datagram header format<BR>--<BR>-- 0 4 8 16 19 24 31<BR>-- ---------------------------------------------------------------------------------------------<BR>-- | Version | *Header | Service Typpe | Total Length including header |<BR>-- | (4)
| Length | (ignored) | (in bytes) |<BR>-- ---------------------------------------------------------------------------------------------<BR>-- | Identification | Flags | Fragment Offset |<BR>-- |  
; | | (in 32 bit words) |<BR>-- ---------------------------------------------------------------------------------------------<BR>-- | Time To Live | Protocoll | Header Checksum |<BR>-- | (ignored) | &
nbsp; | |<BR>-- ---------------------------------------------------------------------------------------------<BR>-- | Soource IP Address &n
bsp; |<BR>-- | |<BR>-- ---------------------------------------------------------------------------------------------<BR>-- | Desttination I
P Address |<BR>-- | |<BR>-- ---------------------------------------------------------------------------------------------<BR>-- | &nbs
p; Options (iff any - ignored) | Padding |<BR>-- | | (if needed) |<BR>-- -----------------------------------------------------------
----------------------------------<BR>-- | Data |<BR>-- | &nb
sp; |<BR>-- ---------------------------------------------------------------------------------------------<BR>-- | .... |<BR>-- |  
; |<BR>-- ---------------------------------------------------------------------------------------------<BR>--<BR>-- * - in 32 bit words </P>
<P> process (presState, returnState, cnt, frameDataLatch, datagramLen, headerLen, dataLen, newFrame, wrCnt,<BR> complete, frameType, checksum, targetIP, bufferSelectSig, targetIdent,<BR> position0, position1, ident0, ident1, fragmentOffset, moreFragments, timeout0, timeout1,<BR> endFrame, newFrameByte, frameValid)<BR> begin<BR> -- signal defaults<BR> wrRAM <= '0';<BR> wrData <= (others => '0');<BR> wrAddr <= (others => '0');<BR> datagramSize <= (others => '0');<BR> incCnt <= '0';<BR> rstCnt <= '0';<BR> incWrCnt <= '0';<BR> rstWrCnt <= '0';<BR> newDataGram <= '0';<BR> -- the following two signals remember their previous value if not reassigned<BR> nextHeaderLen &l
t;= headerLen;<BR> nextDatagramLen <= datagramLen;<BR> doWrite <= '0';<BR> getNewByte <= '0';<BR> latchFrameData <= '0';<BR> shiftInSourceIP <= '0';<BR> shiftInTargetIP <= '0';<BR> latchProtocol <= '0';<BR> newHeader <= '0';<BR> newByte <= '0';<BR> inByte <= (others => '0');<BR> latchMoreFragments <= '0';<BR> shiftInFragmentOffset <= '0';</P>
<P> shiftInIdentification <= '0'; <BR> nextBufferSelect <= bufferSelectSig;<BR> latchIdent <= '0';<BR> resetIdent <= '0';<BR> updatePosition <= '0';<BR> resetPosition <= '0';<BR> resetTimeout <= '0';<BR> <BR> case presState is<BR> when stIdle =><BR> -- wait for the arrival of a new frame that has a frameType of 1<BR> if newFrame = '0' or frameType = '0' then<BR> nextState <= stIdle;<BR> else<BR> -- reset the counters for the next datagram<BR> rstCnt <= '1';<BR> rstWrCnt <= '1';<BR> newHeader <= '1';<BR> &nb
sp; nextState <= stGetHeaderLen;<BR> -- get header length and version information<BR> getNewByte <= '1';<BR> end if;</P>
<P> when stGetHeaderLen =><BR> -- check ip version<BR> if frameDataLatch (7 downto 4) /= 4 then<BR> nextState <= stIdle;<BR> else<BR> nextState <= stGetHeaderByte;<BR> -- send data to checksum machine<BR> inByte <= frameDataLatch;<BR> newByte <= '1';<BR> -- get the header length in bytes, rather than 32-bit words<BR> nextHeaderLen <= frameDataLatch (3 downto 0) & "00";<BR> end if;<BR> <BR> when stGetHeaderByte =><BR> -- if we've finished getting the headers and processing them, start on the data<BR>&n
bsp; -- once finished, refragmenting will come next<BR> if cnt = headerLen then<BR> -- only operate on data meant for us, or broadcast data<BR> if checksum = 0 and (targetIP = DEVICE_IP or targetIP = x"FFFFFFFF") then<BR> <BR> -- determine which buffer should be used to handle the data<BR> if ident0 = targetIdent and timeout0 /= FULLTIME then<BR> -- the ident matches and the timeout counter has not expired<BR> nextBufferSelect <= '0';<BR> -- accept the frame if its offset matches what we think it should be<BR> -- this drops out
of order and duplicate frames.<BR> if position0 = fragmentOffset & "000" then<BR> nextState <= stGetDataByte;<BR> else<BR> nextState <= stIdle;<BR> end if; <BR> elsif ident1 = targetIdent and timeout1 /= FULLTIME then<BR> -- the ident matches and the timeout counter has not expired <BR> nextBufferSelect <= '1';<BR> -- accept the frame if its offset matches what we think it should be<BR> &nb
sp; -- this drops out of order and duplicate frames.<BR> if position1 = fragmentOffset & "000" then<BR> nextState <= stGetDataByte;<BR> else<BR> nextState <= stIdle;<BR> end if; <BR> elsif (ident0 = 0 or timeout0 = FULLTIME) and fragmentOffset = 0 then<BR> -- The ident doesn't match either of the buffers so check if buffer 0<BR> -- is free. If ident = 0 or the timeout has expired then the buffer is free<BR> &n
bsp;-- This must be the first fragment if it is to go here so also check the offset<BR> nextState <= stGetDataByte;<BR> nextBufferSelect <= '0';<BR> elsif (ident1 = 0 or timeout1 = FULLTIME) and fragmentOffset = 0 then<BR> -- The ident doesn't match either of the buffers so check if buffer 1<BR> -- is free. If ident = 0 or the timeout has expired then the buffer is free<BR> -- This must be the first fragment if it is to go here so also check the offset<BR> nextState <= stGetDataByte;<BR> nextBufferSelect <= '1';<BR> e
lse<BR> nextState <= stIdle;<BR> end if;<BR> else<BR> -- ignore frame as it wasn't for us<BR> nextState <= stIdle;<BR> end if;<BR> <BR> -- otherwise get the next header byte from RAM<BR> else<BR> nextState <= stStoreHeaderByte;<BR> getNewByte <= '1';<BR> end if;<BR> <BR> when stStoreHeaderByte =><BR> nextState <= stGetHeaderByte;<BR> -- operate on each value of the header received according to count<BR> -- c
ount will be one higher than the last byte received, as it is incremented<BR> -- at the same time as the data is streamed in, so<BR> -- when the data is seen to be available, count should also be one higher<BR> <BR> -- Send data to checksum process<BR> newByte <= '1';<BR> inByte <= frameDataLatch;<BR> <BR> -- Operate on data in the header<BR> case cnt(4 downto 0) is <BR> when "00011" =><BR> nextDatagramLen (10 downto 8) <= frameDataLatch (2 downto 0);<BR> when "00100" =><BR> nextDatagramLen (7 downto 0) <= frameDataL
atch;<BR> when "00101" | "00110" =><BR> shiftInIdentification <= '1';<BR> when "00111" =><BR> shiftInFragmentOffset <= '1';<BR> latchMoreFragments <= '1';<BR> when "01000" =><BR> shiftInFragmentOffset <= '1';<BR> when "01010" =><BR> latchProtocol <= '1';<BR> when "01101" | "01110" | "01111" | "10000" =><BR> shiftInSourceIP <= '1';<BR> when "10001" | "10010" | "10011" | "10100" => <BR> shiftInTargetIP <= '1';
<BR> when others =><BR> end case;<BR> <BR> when stGetDataByte =><BR> -- if we haven't finished receiving the data, then<BR> if cnt /= datagramLen then<BR> nextState <= stSetupWriteDataByte;<BR> -- read an IP data byte from the data stream...<BR> getNewByte <= '1';<BR> elsif endFrame = '1' and frameValid = '1' then<BR> -- this means that the frame is finished and was valid<BR> -- so update the buffer data and go to final state<BR> nextState <= stCompleteFragment;<BR> resetTimeout <= '1'; -- start/restart timer<BR
> latchIdent <= '1'; -- allocate buffer to data<BR> if fragmentOffset = 0 then -- check if this is the first fragment<BR> resetPosition <= '1'; -- give position initial value<BR> else<BR> updatePosition <= '1'; -- or add to the amount of data stored<BR> end if;<BR> elsif endFrame = '1' then<BR> -- the frame is complete but not valid so ignore it<BR> nextState <= stIdle;<BR> else<BR> -- the frame is not complete so keep looping until it is<BR> nextState <= stGetDataByte;<BR> end if
;<BR> <BR> when stSetupWriteDataByte =><BR> nextState <= stGetDataByte;<BR> --Set up to write the byte that was read in stGetDataByte to RAM<BR> doWrite <= '1';<BR> wrData <= frameDataLatch;</P>
<P> when stCompleteFragment =><BR> -- Signal the transport protocols if the datagram is finished<BR> -- or await next frame.<BR> nextState <= stIdle;<BR> if moreFragments = '0' then<BR> -- Last frame so :<BR> newDatagram <= '1'; -- notify higher protocols it's ready<BR> resetIdent <= '1'; -- free buffer for next time<BR> if bufferSelectSig = '0' then -- output datagram size from correct buffer<BR> datagramSize <= position0;<BR> else<BR> datagramSize <= position1;<BR> end if;<BR> &
nbsp;end if;<BR> <BR> when stDoWrite =><BR> -- Wait for RAM write request to be serviced<BR> if complete = '0' then<BR> -- keep signals asserted until complete is high<BR> nextState <= stDoWrite;<BR> wrRAM <= '1';<BR> -- The address is based on the fragment offset and buffer<BR> if bufferSelectSig = '0' then<BR> wrAddr <= "001" & (wrCnt + (fragmentOffset & "000"));<BR> else<BR> wrAddr <= "010" & (wrCnt + (fragmentOffset & "000"));<BR> end if;<BR> wrData <= frameDataLatch;
<BR> else<BR> -- when write is finished, go to returnState<BR> nextState <= returnState;<BR> incWrCnt <= '1';<BR> end if;</P>
<P> when stGetNewByte =><BR> if newFrameByte = '0' then<BR> -- wait for new byte to arrive<BR> nextState <= stgetNewByte;<BR> else<BR> -- latch new byte and go to returnState<BR> nextState <= returnState;<BR> incCnt <= '1';<BR> latchFrameData <= '1';<BR> end if;<BR> when others =><BR> end case;<BR> end process;<BR> <BR> -- Perform 2's complement to one's complement conversion, and invert output<BR> checksumInt <= checksumLong(15 downto 0) + checksumLong(16);<BR> checksum <= NOT checksumInt;</P>
<P> process (clk,rstn)<BR> begin<BR> if rstn = '0' then<BR> checkState <= stMSB;<BR> latchMSB <= (others => '0');<BR> checkSumLong <= (others => '0');<BR> lastNewByte <= '0';<BR> elsif clk'event and clk = '1' then<BR> -- this is used to check only for positive transitions<BR> lastNewByte <= newByte; <BR> <BR> case checkState is<BR> when stMSB =><BR> if newHeader = '1' then<BR> -- reset calculation<BR> checkState <= stMSB;<BR> checkSumLong <= (others => '0');<BR> elsif newByte = '1' and lastNewByte
= '0' then<BR> -- latch MSB of 16 bit data<BR> checkState <= stLSB;<BR> latchMSB <= inByte;<BR> else<BR> checkState <= stMSB;<BR> end if;<BR> when stLSB =><BR> if newHeader = '1' then<BR> -- reset calculation<BR> checkState <= stMSB;<BR> checkSumLong <= (others => '0');<BR> elsif newByte = '1' and lastnewByte = '0' then<BR> -- add with 2's complement arithmetic (convert to 1's above)<BR> checkState <= stMSB;<BR>&nbs
p; checkSumLong <= ('0' & checkSumInt) + ('0' & latchMSB & inByte);<BR> else<BR> checkState <= stLSB;<BR> end if;<BR> when others =><BR> checkState <= stMSB;<BR> end case;<BR> end if;<BR> end process; <BR>end internet_arch;</P>
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