Maintain Active Clock Signal

Zellal, 
First inspection of the simulation waveform ,informs that the main
"clock" in your state machine is not active after 1us interval.This is
enough to stop the progress of the Statemachine.
Try to run the simulation for longer time interval with the main clock
"W_CLK" active not constant low"0" as shown in the simulation waveform.
Hope this would help .
Thanks 
Best Regards,

Mohamed A.Salem
Handasa Arabia Co-Founder
www.handasarabia.org


On Sat, 2004-02-14 at 10:18, Zellal B wrote:
> 
> 
>  brother Mohamed,
> 
> i would like to have a remark on my output simulation....the module am
> doing right now has 9 state machine...but when i try to run it, it
> only runs till the second state and it stop....would be able to help
> me.....i had attached the simulation output as a printScreen.....
> 
> 
> 
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> Message number 82


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Message number 83