Design Tasks

Dear all,

I saw that there are many interested people want to join the development so
I'd like ot divide the tasks and please select the one that is suitable for
you.

* HDL code (Verilog or VHDL)
Complexity (4 the simplest and 1 is the hardest according to my estimation)
 - FEC  (Complexity rate 4)
 - HEC(Complexity rate 4)
 - CRC (Complexity rate 4)
 - Correlator (Complexity rate 3)
 - Scrambler (Complexity rate 4)
 - hoping (Complexity rate 1)
 - Encryption (Complexity rate 1)
 - Access code generator (Complexity rate 3)
 - Clock management (Complexity rate 2)
 - Tx & RX Buffers (Complexity rate 2)
 - System controller (Complexity rate 1)
 - Registers (Complexity rate 3)
 - Wishbone interface (Complexity rate 3)

I think we will have more cores in the future

* Bluetooth Emulator should be defined

* Baseband driver that controls the registers and defines standard interface
for other layers. I think this should be written in ANSI C so as to be
portable for all OSs.

* LMP layer code that uses the lower layer driver and generate another
interface for programers to simuly handle the LMP operations.

* I think we can discuss Higher bluetooth layers if anyone intersted in
porting existing tools to our design.

* Design review and compliant to latest standards and implementations and
update the design document accordingly



I hope that anyone intersted in working on any part inform us on the mailing
list so as not have duplicate work


Best regards,
Jamil Khatib

ps.  Happy Ramadan for All

--------------------------
NOUR Mailing List
Handasa Arabia Organization
http://www.handasarabia.org
[email protected]

Message number 84