RE: Design Tasks

Hi,

I used to work for Ericsson, and was a VHDL engineer for Ericsson's BT
development. That makes it difficult for me to get involved with coding for
Nour.

The Ericsson BT design was based on a very accurate 4 MHz Clock and
everything on the baseband was derived from this. I read on your spec that
you will only support 3 PCM Slots (Voice). There is also a fourth for PCM
Data. The voice codec uses raw, A Law, U Law and CVSD encoding schemes. The
A Law and U Law codec functions would be simple (a small look up table).
CVSD more complex.

Also I would recomend that you use a simple processor (Such as the PIC 16..
core) on Opencores to perform much of the Bluetooth control functions, since
this is where you will get into a great deal of trouble. It's easier to
code, and debug a control alg. in some assembler or C code than a large and
clumsy VHDL state machine.

One way for distributed development to work would be to use the foriegn
language interface to Modelsim, or other type of VHDL/Verilog simulator,
executable model, or even physical hardware.

By using the simulator hooked into C or Java TCP/IP sockets you can simulate
point to point or multipoint scenarios using your behavioural or rtl
simulations. This was an idea initialy developed by a coleague (Russel) but
it was used very late in the development after the first chips were being
verified, and so was not used extensively. I think it would be very usefull
for the Nour project though.

I am thinking of creating prototyping cards, similar concept to XESS, and
some of the earlier Opencore boards.

My versions will include the Analogue Phy's for Ethernet, USB, and a Class 1
or 2 Bluetooth Radio. I intend to try to do this for an income (I am
unemployed since Ericsson and Infineon closed my design centre). If I
include the digital Phy (Baseband) devices on the boards, I will provide the
options of bypassing the physical hardware for virtual hardware in the FPGA.

Pleas could you give me feedback for what features you might want on a
prototype platform, and what cost you could afford for such a board.

Regards

Mike


-----Original Message-----
From: Jamil Khatib [mailto:[email protected]]
Sent: 03 November 2003 07:28
To: [email protected]
Subject: Re: [NOUR] Design Tasks



Hi,
Sorry for the delay. It seems that we have to prepare some arrangment before
we are able to upload the files to teh site.
Anyhow if you are interested you can contrinue working with teh rest of the
cores as defined in the nour spec.

Regards,
Jamil khatib

On 10/27/2003, "Puloma Mukherjee" <[email protected]> wrote:

>Hi Jamil,
>the FEC,CRC and HEC blocks I have already made,I can proceed to make teh
>correlator,access code generator and encryption if it is alright with
>everyone...please let me know...
>
>On Sun, 26 Oct 2003, Jamil Khatib wrote:
>
>>
>> Dear all,
>>
>> I saw that there are many interested people want to join the development
so
>> I'd like ot divide the tasks and please select the one that is suitable
for
>> you.
>>
>> * HDL code (Verilog or VHDL)
>> Complexity (4 the simplest and 1 is the hardest according to my
estimation)
>>  - FEC  (Complexity rate 4)
>>  - HEC(Complexity rate 4)
>>  - CRC (Complexity rate 4)
>>  - Correlator (Complexity rate 3)
>>  - Scrambler (Complexity rate 4)
>>  - hoping (Complexity rate 1)
>>  - Encryption (Complexity rate 1)
>>  - Access code generator (Complexity rate 3)
>>  - Clock management (Complexity rate 2)
>>  - Tx & RX Buffers (Complexity rate 2)
>>  - System controller (Complexity rate 1)
>>  - Registers (Complexity rate 3)
>>  - Wishbone interface (Complexity rate 3)
>>
>> I think we will have more cores in the future
>>
>> * Bluetooth Emulator should be defined
>>
>> * Baseband driver that controls the registers and defines standard
interface
>> for other layers. I think this should be written in ANSI C so as to be
>> portable for all OSs.
>>
>> * LMP layer code that uses the lower layer driver and generate another
>> interface for programers to simuly handle the LMP operations.
>>
>> * I think we can discuss Higher bluetooth layers if anyone intersted in
>> porting existing tools to our design.
>>
>> * Design review and compliant to latest standards and implementations and
>> update the design document accordingly
>>
>>
>>
>> I hope that anyone intersted in working on any part inform us on the
mailing
>> list so as not have duplicate work
>>
>>
>> Best regards,
>> Jamil Khatib
>>
>> ps.  Happy Ramadan for All
>>
>> --------------------------
>> NOUR Mailing List
>> Handasa Arabia Organization
>> http://www.handasarabia.org
>> [email protected]
>>
>> Message number 84
>>
>>
>
>
>--------------------------
>NOUR Mailing List
>Handasa Arabia Organization
>http://www.handasarabia.org
>[email protected]
>
>Message number 85

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