Re: cores status /uclinux port

Good news.
For me I am still working on the code of the wishbone to parallal port bridge
but do not have time to test it on the board. I will try my best this
weekend

Regards,
Jamil
On 10/15/2003, "Soban Shoeb Chawre" <[email protected]> wrote:

>msalem wrote:
>>
>> What is the status of the cores under development.---for Jamil
>> and Soban ..
>Hello All,
>
>I have completed coding for Single Read/Write cycles.I'll mail the
>documentation and code on Sunday.
>
>Regards,
>-Soban.
>> *Other participants, please let us discuss the porting of Uclinux
>> assuming that our memory cores and wishbone interfaces are ready.
>> The OFOQ prototypoe board has a JTAG interface. So let us start
>> some ideas about the Porting ...
>> Best Regards,
>> Mohamed A.Salem
>> Handasa Arabia Organization
>> www.handasarabia.org
>>
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>> http://www.handasarabia.org
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>>
>> Message number 113
>
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>Message number 114

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