Re: Memory Controller

Salem,

I was referring to memory controller in Open RISC SOC on the
opencores.org website...





Mohamed Salem wrote:
> 
> Soban ,
> Referring to the memory controller IP core
> http://www.opencores.com/projects/mem_ctrl/
> The features shows that it is supporting :
> 
> SDRAM, SSRAM, FLASH, ROM and many other devices supported
> SO why we do need to design our own for an SSRAM...
> If u have investigated the subject from a close look that would prove
> the suggestion of building our own for the SSRAM let me know in some

> details about it . The main idea about the open source Hardware is built
> on RE-USE of Ready-Made cores and try as possible using it as a
> Black-Box whenever possible in order to speed up the development
> cycle.If you some particular technical reasons about not using the IP
> core mentioned above , please state them, then we can decide to start
> the cycle from the beginning in order to build the SSRAM interface.
> 
> Thanks man for your effort ... keep up the good work..
> 
> Best Regards,
>         Mohamed A. Salem
> 
> On Wed, 2003-07-16 at 19:43, Soban Shoeb Chawre wrote:
> > Hello Salem,
> >
> > Yes if we are going to use SDRAM memory (I think we will need SDRAM for
> > main memory of system, SSRAM will be used for cache and Flash for
> > booting and other apllications...) then we need to model that also.
> >
> > I have studied and downloaded the SSRAM datasheet and model from Micron
> > website, we have 2 design our own SSRAM interface we cannot use the
> > opencores interface.
> >
> > -Regards,
> > Saoban
> >
> >
> >
> > Mohamed Salem wrote:
> > >
> > > Soban ,
> > > I have to let you know that the SOPC of Altera Board has the APEX device
> > > as its core . The memory section describes the memory on the board as
> > > follows :
> > > ==========
> > > Memory
> > >
> > > **To support processor functions implemented in the APEX device, the
> > >
> > > board includes a memory system consisting of the following:
> > >
> > > * Non- Volatile memory: 64 Mbytes of synchronous DRAM, organized as
> > >
> > > 8 Mbytes 64 Mbytes
> > >
> > > * Non-volatile memory: 4 Mbytes Flash memory and a 256-Kbyte
> > >
> > > EPROM memory
> > >
> > > * Pipelined cache memory with burst SRAM organized as
> > >
> > > 256 Kbytes 32 Kbytes.
> > > ==========
> > > most likely we will need an SDRAM memory model if this is the case as
> > > mentioned above . What do u think in the light of the aforementioned
> > > info about the board memories .
> > > Waiting for your comments ..
> > >
> > > Thanks ..
> > > Best Regards,
> > >
> > >         Mohamed A. Salem
> > >
> > > On Thu, 2003-07-10 at 22:13, Soban Shoeb Chawre wrote:
> > > > Hello All,
> > > >
> > > > The core for SRAM controller in the openrisc soc is meant for SRAM
> > > > memory bank that is there on XESS board.
> > > >
> > > > We will b porting the design on the Altera SOPC board which has Micron
> > > > SSRAM MT8L256L32DT
> > > >
> > > > If any 1 of u can plz give me links for the datasheet (have searched at
> > > > micron website...).
> > > >
> > > > Regards,
> > > > -Soban
> > > > -------------------------------------------------------------------
> > > > "Allaahummaa laa aa'ishaa illal  aa'ish-ul-aakhiraah.
> > > >  Fagfiral Ansaaraa wal muhaajiraah."
> > > > -------------------------------------------------------------------
> > > >
> > > >
> > > >
> > > >
> > > >
> > > > Mohamed Salem wrote:
> > > > >
> > > > > Hi all ,
> > > > >         This message is addressing starting a technical aggressive plan to get
> > > > > the Memory controller part of OFOQ working asap.
> > > > >
> > > > > PLease , Have a look right now on the block diagram of the system in
> > > > > page 5 of the specs.
> > > > >
> > > > >         The objective is to :
> > > > >
> > > > > Integrate the memory controller IP core of (opencores) with the
> > > > > SRAM/FLASH from one side, and to the Wish-bone Interface from the other
> > > > > side (as shown in the diagram).
> > > > >         Then the wish-bone is interfacing with the openRisc CPU ..
> > > > > We need to choose a SRAM/FLASG model to be used in testing.
> > > > >         We need to be at first to be as simple as possible until we verify the
> > > > > concept then we can start complicating the components.
> > > > >         We need also to test the whole flow and communication between all
> > > > > involved components with a test bench for this purpose.
> > > > >
> > > > > {{OpenRISC <==> Wish-Bone <<==>> Memory controller <<===>>SRAM/FLASH..}}
> > > > >
> > > > > We need to study the features of the memory controller and how to
> > > > > connect it to the other system parts. The cores are available, what we
> > > > > need is to think how to STITCH them and then with a test bench check the
> > > > > flow of data and communication between those system parts.
> > > > >
> > > > > Interested peers in this part should push the flow ..
> > > > >
> > > > > Guys , I'll drive a very tight plan for OFOQ in the next few months.
> > > > > Active interested guys who were  waiting, please show up .. We wanna
> > > > > come out with it as soon as possible .. Many folks around are waiting
> > > > > for a REAL working prototype for OFOQ PDA..
> > > > >
> > > > > Best Regards,
> > > > >
> > > > >         Mohamed A. Salem...
> > > > >
> > > > > --
> > > > > Mohamed A Salem
> > > > > Handasa Arabia Organization
> > > > > www.handasarabia.org
> > > > >
> > > > > ---------------------------------------------------------------------
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> > > > > For additional commands, e-mail: [email protected]
> > > > > Handasa Arabia, http://www.handasarabia.org
> > > --
> > > Mohamed A Salem
> > > Handasa Arabia Organization
> > > www.handasarabia.org
> --
> Mohamed A Salem
> Handasa Arabia Organization
> www.handasarabia.org