Re: some work to be done

Good Jamil, 
I had already make a survey about the memory controller before getting
some how busy with the last press .. Now, It is so helpful to resume to
task again with the notes mentioned ur mail .. 
I'll investigate the issue in details and get back to you soon.. The
memory controller is a mile-stone right now .. 
Thanks ..
Best Regards,
Mohamed A.Salem 

On Tue, 2003-08-26 at 16:32, Jamil Khatib wrote:
> Hi,
> Since there is no much advancement in the memory controller I'd like to
> provide this task for anyone interested to contrinue in this issue.
> 
> We need an SRAM controller for the two SRAMs on Altera SOPC board
> 
> - I suggest to visit
> http://www.opencores.org/cvsweb.shtml/or1k/xess/xsv_fpga/ where you can
> download the port of the OR1k to XSV board both the documentation and rtl
> code
> 
> - check the sram_top file which is a a bridge between wishbone and on board
> SRAMs
> 
> - You can find hte datasheet of the XSV SRAMs on the above link and you can
> download the SRAM datasheet of the Altera SOPC board. (if you can not find
> the datasheets let me know)
> 
> - Try to compare what sram_top file and what we need to do the bridge for our
> board.
> 
> - I made found some points but I'd like to get your conclusions first.
> 
> - We need to write the code (VHDL or verilog)
> 
> - I am going to work now on a test core to test wishbone cores through PC
> parallel port. 
> 
> Please let me know if you need more information and let us do the SRAM
> controller first and test it before connecting it to the CPU
> 
> Best regarsd,
> Jamil KHatib
> 
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> Message number 70


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