Re: SRAM On Board- Document

Salam,
Is there anyone interested in coding the wishbone to SRAM bridge?

Regards,
Jamil
On 9/16/2003, "soban shoeb chawre" <[email protected]> wrote:

>
>Salaam All,
>
>Mohamed Salem wrote:
>>
>>Dear All,
>>         I have compiled a document about the SSRAM memory on the
>>SOPC"System On
>>Programmable Chip" Board. It provides the required information
>>for the
>>memory controller core design. The SSRAM will be used as our
>>"main
>>memory". The document can be found at:
>>http://www.handasarabia.org/document.php?id=3D103
>>The document has some queries. Please provide your answers as
>>possible.
>
>The parity option for the SSRAM was not connected.
>"***I have here a question for readers .what is the parity option
>in
>SSRAM? Reply on the list ..Thanks in advance ."
>
>SSRAMs are also  available with parity option, in which there is
>a
>parity pin (bit) corresponding to each byte of the data bus.
>
>In our case we have 32 bits wide data bus, so there would have
>been 4
>parity bits.
>
>However, since our SSRAM is x32 version and not x36 version,
>these
>4 pins are NF i.e. no function.And hence these pins are not
>connected.
>
>Question: Any one who has knowledge about the timing analysis of
>the
>SSRAM please provide it to us on the project mailing list.Thanks
>in
>advance .
>
>Please tell me specifically what kind of inforamtion is needed.
>I'll surely share if I know.
>
>
>>
>>         Download the SRAM memory controller "Verilog file" which
>>was used for a
>>similar SRAM on XESS board.
>>http://www.opencores.org/cvsweb.shtml/or1k/orp/orp_soc/rtl/verilog/mem_if/s=
ram_top.v
>>         This file could be manipulated to achieve our own SRAM
>>interface or we
>>could use it as a reference while building our own in "VHDL
>>and/or
>>Verilog".
>
>I think it will be better if we study the SSRAM part of memory
>Controller and try to tune it for our requirement.Bcoz this
>'SSRAM' and
>not 'SRAM'.
>
>>
>>on another note:
>>         I'd like all of us to have a look on the ORPsoc project
>> from Opencore
>>which is a complete simulation environment for System On Chip
>>based on
>>Open Risc Processor. It has software packages and hardware cores.
>>It is
>>not just a simulation environment but it can be customized to a
>>close
>>vision to what we need for OFOQ system.
>>The link is :
>>http://www.opencores.org/projects/or1k/ORPsoc
>>"OpenRisc Reference Platform for SoC"
>>
>>         Thanks all for your time and Contribution.
>>
>>Best Regards,
>>
>>--
>>Mohamed A.Salem
>>Handasa Arabia Organization
>>www.handasarabia.org
>>
>>-------------------------------
>>OFOQ Mailing List
>>Handasa Arabia Organization
>>http://www.handasarabia.org
>>[email protected]
>>
>>Message number 100
>
>
>regards,
>-Soban.
>
>
>
>
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>Message number 102

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Message number 104