Re: SRAM On Board- Document

Ok...got it, you r going to load the SRAM
 from parellel port using WB burst write
or (many single write) cycles, while holding the
processor in reset.

Thanx for prompt reply.



Jamil Khatib wrote:
>
>Soban,
>I mean that we need to convert wishbone transactions (read,write 
>and so) to
>SRAM transactions.
>SRAM  <--> WISHBONE
>so that whenever I write a byte to wishbone it is written to the 
>SRAM and
>when I read one from the wishbone it is read actually from the 
>SRAM.
>
>The block has no relation with the boot strapper. I am working 
>now on core
>that writes to from the parallel port to WISHBONE bus so when 
>everything is
>done we can connect both cores to write to the SRAM from the PC
>
>PP <--> WISHBONE
>
>final core should look like
>
>SRAM <-->WISHBONE<--> PP
>
>hope this helps
>Regards,
>Jamil
>
>On 9/16/2003, "soban shoeb chawre" <[email protected]> 
>wrote:
>
> ><Salam,
> ><Is there anyone interested in coding the wishbone to SRAM
> >bridge?
> >
> ><Regards,
> ><Jamil
> >
> >WS,
> >
> >First of all sorry for all those mails.
> >
> >...actually my composer got stuck when i was sending mails
> >
> >I am interested in doing that..
> >
> >Jameel, i'd like know by "bridge" do u mean  boot strapper (i 
>mean
> >ckt
> >to load SSRAM from parellel port while keeping everything 
>reset)
> >and controller?
> >
> >...or only bootstrapper?
> >
> >or is it that you have already made bloock diagram for boot
> >strapper on which you were already working, and are looking 
>for
> >some1 to code ?
> >
> >
> >plz let me know
> >
> >
> >Soban.
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
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>Message number 106



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Message number 107