please help me in CS604

  please send me the solution of the following question of CS604 Please send me 
  Question #1
  Consider a computer system with the following specifications and answer the questions that follow. The system uses a cache (TLB) to contain part of the page table for a process. 
  CPU = 3.0 GHz P4 HT
  Paging Size Disk =120 GB
  RAM Size =1 GB
  Maximum Process Size = 256 MB
  Page Size =4 KB
  Page Table Entry Size =4 bytes
  Cache (TLB) Access Time =10 nanoseconds 
  Memory Access Time =100 nanoseconds
  Cache Hit Ratio =95%
  
  a. (4 Points) what are the sizes of physical address and physical address space?
  Physical Address:
  Physical Address Space:
  b. (4 Points) what are the sizes of logical address and logical address space?
  Logical Address:
  Logical Address Space:
  c. (2 Point) what is the size (in bytes) of the page table?
  d. (3 Points) How many levels of paging does the system support? Why? Show the break down of the logical address in the form of pi 's and d. Clearly show the number of bits needed for d and each pi .
  e. (3 Point) If page 7 of a process is stored in frame 126 and the process generates the logical address (7, 16), show logical and physical addresses in the form of 1s and 0s?
  f. (4 Points) what is the effective memory access time for the system?
  Question #2
  Consider a file currently consisting of 100 blocks. Assume that the PCB, bit vector block, index block (in case of indexed allocation), and directory block are in the main memory. Calculate the number of I/O operations required to add a new block in the middle of the file for contiguous, linked, and indexed allocation techniques. For contiguous allocation, assume that there is no room to grow in the beginning or end of file. Also assume that block information to be added is in a kernel buffer
  Contiguous Allocation:
  Linked Allocation:
  Indexed Allocation:
  Question #3 
  Consider a pure demand paging system with a paging disk that has an average access and transfer time of 20 milliseconds. Addresses are translated through a page table in main memory, with an access time of 50 nanoseconds per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added cache memory that reduces access time to one memory reference, if page table entry is in the cache. Assume that cache access time is negligible. 
  Assume that 80% of the accesses are in the cache, of the remaining, 10% cause page faults, and 50% of the replaced pages are dirty. Write down the expression / equation for the effective memory access time for the computer system. Show your work.
  When a soft link is created in UNIX the ln –s command:
      1. A new directory is created.
  2. A new file is created that contains the pathname of the existing file as specified in the command.
  3. The inode number in the directory entry for the existing file and that of the link file are different 
  4. All of the above
  5. None of the above
  A system call
      1. Is an entry point into the kernel code?
  2. Allows a program to request a kernel service.
  3. Is a technique to protect I/O devices and other system resources.
  4. All of the above
  5. None of the above
  A system uses a page size of 8KB and has 512MB RAM. If it allows a maximum process size to be 64MB, then following is true for the system 
      1. It has 29-bit logical address.
  2. It has 26-bit physical address.
  3. It has 64 k frames
  4. All of the above
  5. None of the above
  A page replacement algorithm in a demand paged virtual memory system may suffer from Belady’s Anomaly if 
      1. The number of frames allocated to a processes are increased from three to four
  2. The replacement algorithm does not belong to the class of stack replacement algorithms
  3. The replacement algorithm is not the least recently used algorithm.
  4. All of the above
  5. None of the above
  Semaphore operations, wait and signal, must be performed atomically because
      1. If they are not atomic, the semaphore value may become incorrect.
  2. They are implemented as system calls.
  3. Otherwise busy waiting becomes a problem due to the wasted CPU cycles.
  4. the wait operation increment the value of semaphores by one and signal decrements it by one, we must not allow interleaving of these operation as the semaphores value may become incorrect.
  5. None of the above.

		
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