Re: GSoC: Add SMT/HT awareness to DragonFlyBSD scheduler

Hi,


> Is this correct?
>
> e.g.: CHIP0 has cores 0,1,2,8,9,10 and so does CHIP1,
>   but there is no core labelled 3,4,5,6,7 and 11
> also the cpu numbering seems 'staggered' to me -
>   e.g. chip0/core0/{cpu1,cpu13) and chip1/core0/{cpu0,cpu12}
> rather than something more like:
>   chip0/core0-5/cpu0-11 & chip1/core6-11/cpu12-23
>
There is no standard on how the cpu's are numbered. The cpu1-cpu13,
cpu0-cpu12,etc grouping of HT threads is ok because I tested the HT passive
scheduling (the first part of my project) and it seems to give good
results. The core numbers are extracted from the APICIDs (the core_bits and
logical_bits are ok). We dumped the APICIDs with acpidump and they are ok.
I haven't look much at this issue.

Mihai