Re: Cortex-M3 HAL interrupt-priority code bug

Nagaraj K <[email protected]> writes:

> I see that this function wrongly implements the priority level in
> Cortex-M3 processor. According to the Cortex-M3 data sheet, we need to
> write the priority level to the top N bits of the register where N is
> the number of priority level bits implemented in this particular
> version of the cortex variant.

The intention in the design of the hardware is that software can use a
256 level prioirity scheme on all implementations. By defining the
actual priority in terms of the top N bits of the registers, the
hardware essentially groups the 256 virtual priorities into a set of
real priorities by ignoring the less significant bits.

eCos simply follows the lead given by the hardware and implements 256
priorities. It is a good scheme and allows us to write code that will
work in all implementations.

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Nick Garnett                                      eCos Kernel Architect
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