R: STM32F107 on STM3210C-EVAL

"Gian Maria" <[email protected]>
Newsgroups gmane.os.ecos.devel
Message-ID <3E47EE2FBA0343E9B42A8DF0F8B8F5D9@Mr32bitPC>
I agree with you for HSE configuration, for my opinion this type of settings
that are not common to all STM32 must be put under specific EVB.
Connectivity line is a little bit different respect other STM32.
For my tests I have implemented a new option like

        cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV2 {
            display         "HCLK divider 2"
            flavor          data
            default_value   5
            legal_values    { 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 }
        }

And made a restriction in the EVB to set the right value
 
    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_DIV2 == 5}


In this way I can control the configuration, but I don't have to modify much
the original cdl.

My idea is to make STM3210C-EVAL running with eCos and RedBoot when all is
working I want to upload it, but I'm at the beginning and I have to study a
lot of eCos platform so I don't have a date.

Best regards Gian



-----Messaggio originale-----
Da: [email protected]
[mailto:[email protected]] Per conto di jerzy dyrda
Inviato: lunedì 28 marzo 2011 12:47
A: [email protected]; Gian Maria
Oggetto: Re: STM32F107 on STM3210C-EVAL

Hello all,

On Monday 28 March 2011 11:51:45 [email protected] wrote:
(...)
> There is only one thing left - the RCC differences. In RM there is a
> seperate section about RCC config for CL. But at the first look it seems
> that registers are compatible.
RCC registers are extended to support 2 extra PPL's with appropriate divider
and multiplier.
Main differences is that source of PLL clock it isn't anymore taken directly
from HSE or HSE/2 clock 
but it's introduced new divider PREDIV1 thus PLLSRC bit in RCC_CFGR register
has partially 
different meaning. And another issue is external crystal. It value is 25MHz
not 8 MHz like in 
STM3210E what causes need of using second PLL to produce CPU 72MHz.

HSE == 25MHz   /  PREDIV2 == 5 -> 5MHz   *  PLLMUL2 == 8 ->  
40MHz / PREDIV1 == 5 -> 8MHz * PLLMUL == 9 -> 72MHz = SYSCLK

It's looks ugly but above method it's used in ST source code for STM3210C
evaluation board.

Best regards
jerzy
lmpx.com only provides a reader for public news (NNTP) servers. It is not affiliated with the servers or forums shown here and is not responsible for the content of articles, which is written by their respective authors.