[Bug 1001815] New: Freescale DSPI avoid Rx DMA if transfer fits in FIFO.

Please do not reply to this email, use the link below.

http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001815

            Bug ID: 1001815
           Summary: Freescale DSPI avoid Rx DMA if transfer fits in FIFO.
           Product: eCos
           Version: CVS
            Target: freescale_twr_k70f120m (Freescale Kinetis TWR-K70F120M
                    board)
  Architecture/Host Cortex-M
                OS:
            Status: NEW
          Severity: enhancement
          Priority: low
         Component: Patches and contributions
          Assignee: [email protected]
          Reporter: [email protected]
                CC: [email protected]
        Depends on: 1001814

Created attachment 2157
  --> http://bugs.ecos.sourceware.org/attachment.cgi?id=2157&action=edit
DSPI Rx DMA avoid

Current DSPI avoids Tx DMA when transfer fits in DSPI FIFO (typically 4 bytes).
The submitted patch does the same also for Rx. The benefit should be
considerable especially in cached systems due to avoidance of cache
invalidation.

Additionally the patch implements DSPI clock gating enable as per bug 1001814.

Ilija

-- 
You are receiving this mail because:
You are on the CC list for the bug.