[Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.

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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001815

Ilija Kocho <[email protected]> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Depends on|                            |1001838

--- Comment #7 from Ilija Kocho <[email protected]> ---
In addition the CDL part attachment 2237 complements attachment 2226 of bug
1001838

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