Re: Recent commits reject RPi4B booting: pcib0 vs. pcib1 "rman_manage_region: <pcib1 memory window> request" leads to panic

On 2/14/24 10:16 AM, Mark Millard wrote:
> Top posting a related but separate item:
> 
> I looked up some old (2022-Dec-17) lspci -v output from
> a Linux boot. Note the "Memory at" value 600000000 (in
> the 35 bit BCM2711 address space) and the "(64-bit,
> non-prefetchable)" (and "[size=4K]").
> 
> 01:00.0 USB controller: VIA Technologies, Inc. VL805/806 xHCI USB 3.0 Controller (rev 01) (prog-if 30 [XHCI])
>          Subsystem: VIA Technologies, Inc. VL805/806 xHCI USB 3.0 Controller
>          Device tree node: /sys/firmware/devicetree/base/scb/pcie@7d500000/pci@0,0/usb@0,0
>          Flags: bus master, fast devsel, latency 0, IRQ 51
>          Memory at 600000000 (64-bit, non-prefetchable) [size=4K]
>          Capabilities: [80] Power Management version 3
>          Capabilities: [90] MSI: Enable+ Count=1/4 Maskable- 64bit+
>          Capabilities: [c4] Express Endpoint, MSI 00
>          Capabilities: [100] Advanced Error Reporting
>          Kernel driver in use: xhci_hcd
> 
> 
> "Memory at 600000000 (64-bit, non-prefetchable)":
> Violation of a PCIe standard?

No, this is a device BAR which can be 64-bit (memory BARs can either
be 32-bits or 64-bits).  However, the "window" in a PCI _bridge_ for
memory is only defined to be 32-bits.  Windows in PCI-PCI bridges
are a special type of BAR that defines the address ranges that the
bridge decodes on the parent side and passes down to child devices.
The prefetchable window in PCI-PCI bridges can optionally be 64-bit.

BAR == a range of memory or I/O port addresses decoded by a device,
usually mapped to a register bank, but sometimes mapped to internal
memory (e.g. a framebuffer)

Window == a range of memory or I/O port addresses decoded by a bridge
for which transactions are passed across the bridge to be handled by
a child device.

-- 
John Baldwin