[Differential] D51567: Expand the register definitions for eqos(4)
"peterj (Peter Jeremy)" <[email protected]>
| Newsgroups | gmane.os.freebsd.devel.arm |
|---|---|
| Message-ID | <[email protected]> |
peterj created this revision. peterj added reviewers: ARM, ganbold. Herald added a reviewer: andrew. peterj requested review of this revision. REVISION SUMMARY Expand the register definitions for the eqos(4) controller based on the Rockchip RK3568 TRM Part2 V1.1-20210301.pdf This is now a fairly complete set of definitions as per that TRM. REVISION DETAIL https://reviews.freebsd.org/D51567 AFFECTED FILES sys/dev/eqos/if_eqos_reg.h EMAIL PREFERENCES https://reviews.freebsd.org/settings/panel/emailpreferences/ To: peterj, #arm, ganbold, andrew Cc: freebsd-arm-list
D51567.159218.patch
(text/x-patch, 34.7 KB)
diff --git a/sys/dev/eqos/if_eqos_reg.h b/sys/dev/eqos/if_eqos_reg.h --- a/sys/dev/eqos/if_eqos_reg.h +++ b/sys/dev/eqos/if_eqos_reg.h @@ -36,42 +36,134 @@ #define _EQOS_REG_H #define GMAC_MAC_CONFIGURATION 0x0000 +#define GMAC_MAC_CONFIGURATION_ARPEN (1U << 31) +#define GMAC_MAC_CONFIGURATION_IPC (1U << 27) +#define GMAC_MAC_CONFIGURATION_IPG_SHIFT 24 +#define GMAC_MAC_CONFIGURATION_IPG_MASK (7U << GMAC_MAC_CONFIGURATION_IPG_SHIFT) +#define GMAC_MAC_CONFIGURATION_IPG_96 (0U << GMAC_MAC_CONFIGURATION_IPG_SHIFT) +#define GMAC_MAC_CONFIGURATION_IPG_88 (1U << GMAC_MAC_CONFIGURATION_IPG_SHIFT) +#define GMAC_MAC_CONFIGURATION_IPG_80 (2U << GMAC_MAC_CONFIGURATION_IPG_SHIFT) +#define GMAC_MAC_CONFIGURATION_IPG_72 (3U << GMAC_MAC_CONFIGURATION_IPG_SHIFT) +#define GMAC_MAC_CONFIGURATION_IPG_64 (4U << GMAC_MAC_CONFIGURATION_IPG_SHIFT) +#define GMAC_MAC_CONFIGURATION_IPG_56 (5U << GMAC_MAC_CONFIGURATION_IPG_SHIFT) +#define GMAC_MAC_CONFIGURATION_IPG_46 (6U << GMAC_MAC_CONFIGURATION_IPG_SHIFT) +#define GMAC_MAC_CONFIGURATION_IPG_40 (7U << GMAC_MAC_CONFIGURATION_IPG_SHIFT) +#define GMAC_MAC_CONFIGURATION_GPSLCE (1U << 23) +#define GMAC_MAC_CONFIGURATION_S2KP (1U << 22) #define GMAC_MAC_CONFIGURATION_CST (1U << 21) #define GMAC_MAC_CONFIGURATION_ACS (1U << 20) +#define GMAC_MAC_CONFIGURATION_WD (1U << 19) #define GMAC_MAC_CONFIGURATION_BE (1U << 18) #define GMAC_MAC_CONFIGURATION_JD (1U << 17) #define GMAC_MAC_CONFIGURATION_JE (1U << 16) #define GMAC_MAC_CONFIGURATION_PS (1U << 15) #define GMAC_MAC_CONFIGURATION_FES (1U << 14) #define GMAC_MAC_CONFIGURATION_DM (1U << 13) +#define GMAC_MAC_CONFIGURATION_LM (1U << 12) +#define GMAC_MAC_CONFIGURATION_ECRSFD (1U << 11) +#define GMAC_MAC_CONFIGURATION_DO (1U << 10) #define GMAC_MAC_CONFIGURATION_DCRS (1U << 9) +#define GMAC_MAC_CONFIGURATION_DR (1U << 8) +#define GMAC_MAC_CONFIGURATION_BL_SHIFT 5 +#define GMAC_MAC_CONFIGURATION_BL_MASK (3U << GMAC_MAC_CONFIGURATION_BL_SHIFT) +#define GMAC_MAC_CONFIGURATION_BL_10 (0U << GMAC_MAC_CONFIGURATION_BL_SHIFT) +#define GMAC_MAC_CONFIGURATION_BL_8 (1U << GMAC_MAC_CONFIGURATION_BL_SHIFT) +#define GMAC_MAC_CONFIGURATION_BL_4 (2U << GMAC_MAC_CONFIGURATION_BL_SHIFT) +#define GMAC_MAC_CONFIGURATION_BL_1 (3U << GMAC_MAC_CONFIGURATION_BL_SHIFT) +#define GMAC_MAC_CONFIGURATION_DC (1U << 4) +#define GMAC_MAC_CONFIGURATION_PRELEN_SHIFT 2 +#define GMAC_MAC_CONFIGURATION_PRELEN_MASK (2U << GMAC_MAC_CONFIGURATION_PRELEN_SHIFT) +#define GMAC_MAC_CONFIGURATION_PRELEN_7 (0U << GMAC_MAC_CONFIGURATION_PRELEN_SHIFT) +#define GMAC_MAC_CONFIGURATION_PRELEN_5 (1U << GMAC_MAC_CONFIGURATION_PRELEN_SHIFT) +#define GMAC_MAC_CONFIGURATION_PRELEN_3 (2U << GMAC_MAC_CONFIGURATION_PRELEN_SHIFT) #define GMAC_MAC_CONFIGURATION_TE (1U << 1) #define GMAC_MAC_CONFIGURATION_RE (1U << 0) #define GMAC_MAC_EXT_CONFIGURATION 0x0004 +#define GMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT 25 +#define GMAC_MAC_EXT_CONFIGURATION_EIPG_MASK (0x1FU << GMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT) +#define GMAC_MAC_EXT_CONFIGURATION_EIPG_n (nU << GMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT) +#define GMAC_MAC_EXT_CONFIGURATION_EIPGEN (1U << 24) +#define GMAC_MAC_EXT_CONFIGURATION_USP (1U << 18) +#define GMAC_MAC_EXT_CONFIGURATION_SPEN (1U << 17) +#define GMAC_MAC_EXT_CONFIGURATION_DCRCC (1U << 16) +#define GMAC_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFFU << 0) #define GMAC_MAC_PACKET_FILTER 0x0008 +#define GMAC_MAC_PACKET_FILTER_VTFE (1U << 16) #define GMAC_MAC_PACKET_FILTER_HPF (1U << 10) -#define GMAC_MAC_PACKET_FILTER_PCF_MASK (3U << 6) -#define GMAC_MAC_PACKET_FILTER_PCF_ALL (2U << 6) +#define GMAC_MAC_PACKET_FILTER_PCF_SHIFT 6 +#define GMAC_MAC_PACKET_FILTER_PCF_MASK (3U << GMAC_MAC_PACKET_FILTER_PCF_SHIFT) +#define GMAC_MAC_PACKET_FILTER_PCF_NONE (0U << GMAC_MAC_PACKET_FILTER_PCF_SHIFT) +#define GMAC_MAC_PACKET_FILTER_PCF_NO_PAUSE (1U << GMAC_MAC_PACKET_FILTER_PCF_SHIFT) +#define GMAC_MAC_PACKET_FILTER_PCF_ALL (2U << GMAC_MAC_PACKET_FILTER_PCF_SHIFT) +#define GMAC_MAC_PACKET_FILTER_PCF_FILTER (3U << GMAC_MAC_PACKET_FILTER_PCF_SHIFT) #define GMAC_MAC_PACKET_FILTER_DBF (1U << 5) #define GMAC_MAC_PACKET_FILTER_PM (1U << 4) +#define GMAC_MAC_PACKET_FILTER_DAIF (1U << 3) #define GMAC_MAC_PACKET_FILTER_HMC (1U << 2) #define GMAC_MAC_PACKET_FILTER_HUC (1U << 1) #define GMAC_MAC_PACKET_FILTER_PR (1U << 0) #define GMAC_MAC_WATCHDOG_TIMEOUT 0x000C +#define GMAC_MAC_WATCHDOG_TIMEOUT_PWE (1U << 8) +#define GMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xFU << 0) #define GMAC_MAC_HASH_TABLE_REG0 0x0010 #define GMAC_MAC_HASH_TABLE_REG1 0x0014 #define GMAC_MAC_VLAN_TAG 0x0050 +#define GMAC_MAC_VLAN_TAG_EVLRXS (1U << 24) +#define GMAC_MAC_VLAN_TAG_EVLS_SHIFT 21 +#define GMAC_MAC_VLAN_TAG_EVLS_MASK (3U << GMAC_MAC_VLAN_TAG_EVLS_SHIFT) +#define GMAC_MAC_VLAN_TAG_EVLS_NEVER (0U << GMAC_MAC_VLAN_TAG_EVLS_SHIFT) +#define GMAC_MAC_VLAN_TAG_EVLS_PASS (1U << GMAC_MAC_VLAN_TAG_EVLS_SHIFT) +#define GMAC_MAC_VLAN_TAG_EVLS_FAIL (2U << GMAC_MAC_VLAN_TAG_EVLS_SHIFT) +#define GMAC_MAC_VLAN_TAG_EVLS_ALWAYS (3U << GMAC_MAC_VLAN_TAG_EVLS_SHIFT) +#define GMAC_MAC_VLAN_TAG_DOVLTC (1U << 20) +#define GMAC_MAC_VLAN_TAG_ERSVLM (1U << 19) +#define GMAC_MAC_VLAN_TAG_ESVL (1U << 18) +#define GMAC_MAC_VLAN_TAG_VTIM (1U << 17) +#define GMAC_MAC_VLAN_TAG_ETV (1U << 16) +#define GMAC_MAC_VLAN_TAG_VL_MASK (0xFFFFU << 0) #define GMAC_MAC_Q0_TX_FLOW_CTRL 0x0070 #define GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16 +#define GMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK (0xFFFFU << GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT) +#define GMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ (1U << 7) +#define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT 4 +#define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK (7U << GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT) +#define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_4 (0U << GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT) +#define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_28 (1U << GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT) +#define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_36 (2U << GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT) +#define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_144 (3U << GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT) +#define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_256 (4U << GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT) +#define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_512 (5U << GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT) #define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE (1U << 1) +#define GMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA (1U << 0) #define GMAC_MAC_RX_FLOW_CTRL 0x0090 +#define GMAC_MAC_RX_FLOW_CTRL_UP (1U << 1) #define GMAC_MAC_RX_FLOW_CTRL_RFE (1U << 0) #define GMAC_RXQ_CTRL0 0x00A0 #define GMAC_RXQ_CTRL0_EN_MASK 0x3 #define GMAC_RXQ_CTRL0_EN_DCB 0x2 #define GMAC_RXQ_CTRL1 0x00A4 #define GMAC_MAC_INTERRUPT_STATUS 0x00B0 +#define GMAC_MAC_INTERRUPT_STATUS_MDIOIS (1U << 18) +#define GMAC_MAC_INTERRUPT_STATUS_RXSTSIS (1U << 14) +#define GMAC_MAC_INTERRUPT_STATUS_TXSTSIS (1U << 13) +#define GMAC_MAC_INTERRUPT_STATUS_TSIS (1U << 12) +#define GMAC_MAC_INTERRUPT_STATUS_MMCRXIPIS (1U << 11) +#define GMAC_MAC_INTERRUPT_STATUS_MMCTXIS (1U << 10) +#define GMAC_MAC_INTERRUPT_STATUS_MMCRXIS (1U << 9) +#define GMAC_MAC_INTERRUPT_STATUS_MMCIS (1U << 8) +#define GMAC_MAC_INTERRUPT_STATUS_LPIIS (1U << 5) +#define GMAC_MAC_INTERRUPT_STATUS_PMTIS (1U << 4) +#define GMAC_MAC_INTERRUPT_STATUS_PHYIS (1U << 3) +#define GMAC_MAC_INTERRUPT_STATUS_RGSMIIIS (1U << 0) #define GMAC_MAC_INTERRUPT_ENABLE 0x00B4 +#define GMAC_MAC_INTERRUPT_ENABLE_MDIOIE (1U << 18) +#define GMAC_MAC_INTERRUPT_ENABLE_RXSTSIE (1U << 14) +#define GMAC_MAC_INTERRUPT_ENABLE_TXSTSIE (1U << 13) +#define GMAC_MAC_INTERRUPT_ENABLE_TSIE (1U << 12) +#define GMAC_MAC_INTERRUPT_ENABLE_LPIIE (1U << 5) +#define GMAC_MAC_INTERRUPT_ENABLE_PMTIE (1U << 4) +#define GMAC_MAC_INTERRUPT_ENABLE_PHYIE (1U << 3) +#define GMAC_MAC_INTERRUPT_ENABLE_RGSMIIIE (1U << 0) #define GMAC_MAC_RX_TX_STATUS 0x00B8 #define GMAC_MAC_RX_TX_STATUS_RWT (1U << 8) #define GMAC_MAC_RX_TX_STATUS_EXCOL (1U << 5) @@ -81,24 +173,168 @@ #define GMAC_MAC_RX_TX_STATUS_NCARR (1U << 1) #define GMAC_MAC_RX_TX_STATUS_TJT (1U << 0) #define GMAC_MAC_PMT_CONTROL_STATUS 0x00C0 +#define GMAC_MAC_PMT_CONTROL_STATUS_RWKFILTRST (1U << 31) +#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT 24 +#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK (0x1FU << GMAC_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT) +#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPFE (1U << 10) +#define GMAC_MAC_PMT_CONTROL_STATUS_GLBLUCAST (1U << 9) +#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPRCVD (1U << 6) +#define GMAC_MAC_PMT_CONTROL_STATUS_MGKPRCVD (1U << 5) +#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPKTEN (1U << 2) +#define GMAC_MAC_PMT_CONTROL_STATUS_MGKPKTEN (1U << 1) +#define GMAC_MAC_PMT_CONTROL_STATUS_PWRDWN (1U << 0) #define GMAC_MAC_RWK_PACKET_FILTER 0x00C4 #define GMAC_MAC_LPI_CONTROL_STATUS 0x00D0 +#define GMAC_MAC_LPI_CONTROL_STATUS_LPITCSE (1U << 21) +#define GMAC_MAC_LPI_CONTROL_STATUS_LPIATE (1U << 20) +#define GMAC_MAC_LPI_CONTROL_STATUS_LPITXA (1U << 19) +#define GMAC_MAC_LPI_CONTROL_STATUS_PLSEN (1U << 18) +#define GMAC_MAC_LPI_CONTROL_STATUS_PLS (1U << 17) +#define GMAC_MAC_LPI_CONTROL_STATUS_LPIEN (1U << 16) +#define GMAC_MAC_LPI_CONTROL_STATUS_RLPIST (1U << 9) +#define GMAC_MAC_LPI_CONTROL_STATUS_TLPIST (1U << 8) +#define GMAC_MAC_LPI_CONTROL_STATUS_RLPIEX (1U << 3) +#define GMAC_MAC_LPI_CONTROL_STATUS_RLPIEN (1U << 2) +#define GMAC_MAC_LPI_CONTROL_STATUS_TLPIEX (1U << 1) +#define GMAC_MAC_LPI_CONTROL_STATUS_TLPIEN (1U << 0) #define GMAC_MAC_LPI_TIMERS_CONTROL 0x00D4 +#define GMAC_MAC_LPI_TIMERS_CONTROL_LST_SHIFT 16 +#define GMAC_MAC_LPI_TIMERS_CONTROL_LST_MASK (0x3FFU << GMAC_MAC_LPI_TIMERS_CONTROL_LST_SHIFT) +#define GMAC_MAC_LPI_TIMERS_CONTROL_TWT_MASK (0xFFFFU << 0) #define GMAC_MAC_LPI_ENTRY_TIMER 0x00D8 +#define GMAC_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT 3 +#define GMAC_MAC_LPI_ENTRY_TIMER_LPIET_MASK (0x3FFFFU << GMAC_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT) #define GMAC_MAC_1US_TIC_COUNTER 0x00DC +#define GMAC_MAC_1US_TIC_COUNTER_TIC_1US_CNTR_MASK (0xFFFU << 0) #define GMAC_MAC_PHYIF_CONTROL_STATUS 0x00F8 +#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSTS (1U << 19) +#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT 17 +#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK (3U << GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT) +#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_2M5HZ (0U << GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT) +#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_25MHZ (1U << GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT) +#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_125MHZ (2U << GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT) +#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKMOD (1U << 16) +#define GMAC_MAC_PHYIF_CONTROL_STATUS_LUD (1U << 1) +#define GMAC_MAC_PHYIF_CONTROL_STATUS_TC (1U << 0) #define GMAC_MAC_VERSION 0x0110 #define GMAC_MAC_VERSION_USERVER_SHIFT 8 #define GMAC_MAC_VERSION_USERVER_MASK (0xFFU << GMAC_MAC_VERSION_USERVER_SHIFT) #define GMAC_MAC_VERSION_SNPSVER_MASK 0xFFU #define GMAC_MAC_DEBUG 0x0114 +#define GMAC_MAC_DEBUG_TFCSTS_SHIFT 17 +#define GMAC_MAC_DEBUG_TFCSTS_MASK (3U << GMAC_MAC_DEBUG_TFCSTS_SHIFT) +#define GMAC_MAC_DEBUG_TFCSTS_IDLE (0U << GMAC_MAC_DEBUG_TFCSTS_SHIFT) +#define GMAC_MAC_DEBUG_TFCSTS_WAIT (1U << GMAC_MAC_DEBUG_TFCSTS_SHIFT) +#define GMAC_MAC_DEBUG_TFCSTS_PAUSE (2U << GMAC_MAC_DEBUG_TFCSTS_SHIFT) +#define GMAC_MAC_DEBUG_TFCSTS_TX (3U << GMAC_MAC_DEBUG_TFCSTS_SHIFT) +#define GMAC_MAC_DEBUG_TPESTS (1U << 16) +#define GMAC_MAC_DEBUG_RFCFCSTS_SHIFT 1 +#define GMAC_MAC_DEBUG_RFCFCSTS_MASK (3U << GMAC_MAC_DEBUG_RFCFCSTS_SHIFT) +#define GMAC_MAC_DEBUG_RPESTS (1U << 0) #define GMAC_MAC_HW_FEATURE(n) (0x011C + 0x4 * (n)) +#define GMAC_MAC_HW_FEATURE0 0x011C +#define GMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT 28 +#define GMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK (0xFU << GMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT) +#define GMAC_MAC_HW_FEATURE0_ACTPHYSEL_RGMII (1U << GMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT) +#define GMAC_MAC_HW_FEATURE0_SAVLANINS (1U << 27) +#define GMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT 25 +#define GMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK (3U << GMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT) +#define GMAC_MAC_HW_FEATURE0_MACADR64SEL (1U << 24) +#define GMAC_MAC_HW_FEATURE0_MACADR32SEL (1U << 23) +#define GMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT 18 +#define GMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK (0x1FU << GMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT) +#define GMAC_MAC_HW_FEATURE0_RXCOESEL (1U << 16) +#define GMAC_MAC_HW_FEATURE0_TXCOESEL (1U << 14) +#define GMAC_MAC_HW_FEATURE0_EEESEL (1U << 13) +#define GMAC_MAC_HW_FEATURE0_TSSEL (1U << 12) +#define GMAC_MAC_HW_FEATURE0_ARPOFFSEL (1U << 9) +#define GMAC_MAC_HW_FEATURE0_MMCSEL (1U << 8) +#define GMAC_MAC_HW_FEATURE0_MGKSEL (1U << 7) +#define GMAC_MAC_HW_FEATURE0_RWKSEL (1U << 6) +#define GMAC_MAC_HW_FEATURE0_SMASEL (1U << 5) +#define GMAC_MAC_HW_FEATURE0_VLHASH (1U << 4) +#define GMAC_MAC_HW_FEATURE0_PCSSEL (1U << 3) +#define GMAC_MAC_HW_FEATURE0_HDSEL (1U << 2) +#define GMAC_MAC_HW_FEATURE0_GMIISEL (1U << 1) +#define GMAC_MAC_HW_FEATURE0_MIISEL (1U << 0) +#define GMAC_MAC_HW_FEATURE1 0x0120 +#define GMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT 27 +#define GMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK (0xFU << GMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT) +#define GMAC_MAC_HW_FEATURE1_L3L4FNUM_NONE (0U << GMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT) +#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT 24 +#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK (3U << GMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT) +#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_64 (1U << GMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT) +#define GMAC_MAC_HW_FEATURE1_POUOST (1U << 23) +#define GMAC_MAC_HW_FEATURE1_RAVSEL (1U << 21) +#define GMAC_MAC_HW_FEATURE1_AVSEL (1U << 20) +#define GMAC_MAC_HW_FEATURE1_DBGMEMA (1U << 19) +#define GMAC_MAC_HW_FEATURE1_TSOEN (1U << 18) +#define GMAC_MAC_HW_FEATURE1_SPHEN (1U << 17) +#define GMAC_MAC_HW_FEATURE1_DCBEN (1U << 16) #define GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT 14 #define GMAC_MAC_HW_FEATURE1_ADDR64_MASK (0x3U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) #define GMAC_MAC_HW_FEATURE1_ADDR64_32BIT (0x0U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) +#define GMAC_MAC_HW_FEATURE1_ADVTHWORD (1U << 13) +#define GMAC_MAC_HW_FEATURE1_PTOEN (1U << 12) +#define GMAC_MAC_HW_FEATURE1_OSTEN (1U << 11) +#define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6 +#define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK (0x1FU << GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) +#define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_16K (7U << GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) +#define GMAC_MAC_HW_FEATURE1_SPRAM (1U << 5) +#define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK (0x1FU << 0) +#define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_32K (8U << 0) +#define GMAC_MAC_HW_FEATURE2 0x0124 +#define GMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT 28 +#define GMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK (7U << GMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT) +#define GMAC_MAC_HW_FEATURE2_AUXSNAPNUM_1 (1U << GMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT) +#define GMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT 24 +#define GMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK (7U << GMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT) +#define GMAC_MAC_HW_FEATURE2_PPSOUTNUM_NONE (0U << GMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT) +#define GMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT 18 +#define GMAC_MAC_HW_FEATURE2_TXCHCNT_MASK (0xFU << GMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT) +#define GMAC_MAC_HW_FEATURE2_TXCHCNT_1 (0U << GMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT) +#define GMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT 12 +#define GMAC_MAC_HW_FEATURE2_RXCHCNT_MASK (0xFU << GMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT) +#define GMAC_MAC_HW_FEATURE2_RXCHCNT_1 (0U << GMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT) +#define GMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT 6 +#define GMAC_MAC_HW_FEATURE2_TXQCNT_MASK (0xFU << GMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT) +#define GMAC_MAC_HW_FEATURE2_TXQCNT_1 (1U << GMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT) +#define GMAC_MAC_HW_FEATURE2_RXQCNT_MASK (0xFU << 0) +#define GMAC_MAC_HW_FEATURE2_RXQCNT_1 (1U << 0) +#define GMAC_MAC_HW_FEATURE3 0x0128 +#define GMAC_MAC_HW_FEATURE3_ASP_SHIFT 28 +#define GMAC_MAC_HW_FEATURE3_ASP_MASK (3U << GMAC_MAC_HW_FEATURE3_ASP_SHIFT) +#define GMAC_MAC_HW_FEATURE3_ASP_NONE (0U << GMAC_MAC_HW_FEATURE3_ASP_SHIFT) +#define GMAC_MAC_HW_FEATURE3_TBSSEL (1U << 27) +#define GMAC_MAC_HW_FEATURE3_FPESEL (1U << 26) +#define GMAC_MAC_HW_FEATURE3_ESTWID_SHIFT 20 +#define GMAC_MAC_HW_FEATURE3_ESTWID_MASK (3U << GMAC_MAC_HW_FEATURE3_ESTWID_SHIFT) +#define GMAC_MAC_HW_FEATURE3_ESTWID_NONE (0U << GMAC_MAC_HW_FEATURE3_ESTWID_SHIFT) +#define GMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT 17 +#define GMAC_MAC_HW_FEATURE3_ESTDEP_MASK (7U << GMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT) +#define GMAC_MAC_HW_FEATURE3_ESTDEP_NONE (0U << GMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT) +#define GMAC_MAC_HW_FEATURE3_ESTSEL (1U << 16) +#define GMAC_MAC_HW_FEATURE3_FRPES_SHIFT 13 +#define GMAC_MAC_HW_FEATURE3_FRPES_MASK (3U << GMAC_MAC_HW_FEATURE3_FRPES_SHIFT) +#define GMAC_MAC_HW_FEATURE3_FRPES_64 (0U << GMAC_MAC_HW_FEATURE3_FRPES_SHIFT) +#define GMAC_MAC_HW_FEATURE3_FRPBS_SHIFT 11 +#define GMAC_MAC_HW_FEATURE3_FRPBS_MASK (3U << GMAC_MAC_HW_FEATURE3_FRPBS_SHIFT) +#define GMAC_MAC_HW_FEATURE3_FRPBS_64 (0U << GMAC_MAC_HW_FEATURE3_FRPBS_SHIFT) +#define GMAC_MAC_HW_FEATURE3_FRPSEL (1U << 10) +#define GMAC_MAC_HW_FEATURE3_PDUPSEL (1U << 9) +#define GMAC_MAC_HW_FEATURE3_DVLAN (1U << 5) +#define GMAC_MAC_HW_FEATURE3_CBTISEL (1U << 4) +#define GMAC_MAC_HW_FEATURE3_NRVF_MASK (7U << 0) +#define GMAC_MAC_HW_FEATURE3_NRVF_NONE (0U << 0) #define GMAC_MAC_MDIO_ADDRESS 0x0200 +#define GMAC_MAC_MDIO_ADDRESS_PSE (1U << 27) +#define GMAC_MAC_MDIO_ADDRESS_BTB (1U << 26) #define GMAC_MAC_MDIO_ADDRESS_PA_SHIFT 21 +#define GMAC_MAC_MDIO_ADDRESS_PA_MASK (0x1FU << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) #define GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT 16 +#define GMAC_MAC_MDIO_ADDRESS_RDA_MASK (0x1FU << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) +#define GMAC_MAC_MDIO_ADDRESS_NTC_SHIFT 12 +#define GMAC_MAC_MDIO_ADDRESS_NTC_MASK (7U << GMAC_MAC_MDIO_ADDRESS_NTC_SHIFT) #define GMAC_MAC_MDIO_ADDRESS_CR_SHIFT 8 #define GMAC_MAC_MDIO_ADDRESS_CR_MASK (0x7U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) #define GMAC_MAC_MDIO_ADDRESS_CR_60_100 (0U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) @@ -116,8 +352,13 @@ #define GMAC_MAC_MDIO_ADDRESS_C45E (1U << 1) #define GMAC_MAC_MDIO_ADDRESS_GB (1U << 0) #define GMAC_MAC_MDIO_DATA 0x0204 +#define GMAC_MAC_MDIO_DATA_RA (1U << 16) +#define GMAC_MAC_MDIO_DATA_GD_MASK (0xFFFFU << 0) #define GMAC_MAC_CSR_SW_CTRL 0x0230 +#define GMAC_MAC_CSR_SW_CTRL_RCWE (1U << 0) #define GMAC_MAC_ADDRESS0_HIGH 0x0300 +#define GMAC_MAC_ADDRESS0_HIGH_AE (1U << 31) +#define GMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK (0xFFFFU << 0) #define GMAC_MAC_ADDRESS0_LOW 0x0304 #define GMAC_MMC_CONTROL 0x0700 #define GMAC_MMC_CONTROL_UCDBC (1U << 8) @@ -128,9 +369,35 @@ #define GMAC_MMC_CONTROL_CNTSTOPRO (1U << 1) #define GMAC_MMC_CONTROL_CNTRST (1U << 0) #define GMAC_MMC_RX_INTERRUPT 0x0704 +#define GMAC_MMC_RX_INTERRUPT_RXFOVPIS (1U << 21) +#define GMAC_MMC_RX_INTERRUPT_RXLENERPIS (1U << 18) +#define GMAC_MMC_RX_INTERRUPT_RXCRCERPIS (1U << 5) +#define GMAC_MMC_RX_INTERRUPT_RXMCGPIS (1U << 4) +#define GMAC_MMC_RX_INTERRUPT_RXGOCTIS (1U << 2) +#define GMAC_MMC_RX_INTERRUPT_RXGBOCTIS (1U << 1) +#define GMAC_MMC_RX_INTERRUPT_RXGBPKTIS (1U << 0) #define GMAC_MMC_TX_INTERRUPT 0x0708 +#define GMAC_MMC_TX_INTERRUPT_TXGPKTIS (1U << 21) +#define GMAC_MMC_TX_INTERRUPT_TXGOCTIS (1U << 20) +#define GMAC_MMC_TX_INTERRUPT_TXCARERPIS (1U << 19) +#define GMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS (1U << 13) +#define GMAC_MMC_TX_INTERRUPT_TXGBPKTIS (1U << 1) +#define GMAC_MMC_TX_INTERRUPT_TXGBOCTIS (1U << 0) #define GMAC_MMC_RX_INTERRUPT_MASK 0x070C +#define GMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM (1U << 21) +#define GMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM (1U << 19) +#define GMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM (1U << 5) +#define GMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM (1U << 4) +#define GMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM (1U << 2) +#define GMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM (1U << 1) +#define GMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM (1U << 0) #define GMAC_MMC_TX_INTERRUPT_MASK 0x0710 +#define GMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM (1U << 21) +#define GMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM (1U << 20) +#define GMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM (1U << 19) +#define GMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM (1U << 13) +#define GMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM (1U << 1) +#define GMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM (1U << 0) #define GMAC_TX_OCTET_COUNT_GOOD_BAD 0x0714 #define GMAC_TX_PACKET_COUNT_GOOD_BAD 0x0718 #define GMAC_TX_UNDERFLOW_ERROR_PACKETS 0x0748 @@ -145,7 +412,31 @@ #define GMAC_RX_LENGTH_ERROR_PACKETS 0x07C8 #define GMAC_RX_FIFO_OVERFLOW_PACKETS 0x07D4 #define GMAC_MMC_IPC_RX_INTERRUPT_MASK 0x0800 +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM (1U << 29) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM (1U << 27) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM (1U << 25) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM (1U << 22) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM (1U << 17) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM (1U << 13) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM (1U << 11) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM (1U << 9) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM (1U << 6) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM (1U << 5) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM (1U << 1) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM (1U << 0) #define GMAC_MMC_IPC_RX_INTERRUPT 0x0808 +#define GMAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS (1U << 29) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS (1U << 27) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS (1U << 25) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS (1U << 22) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS (1U << 17) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS (1U << 13) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS (1U << 11) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS (1U << 9) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS (1U << 6) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS (1U << 5) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS (1U << 1) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS (1U << 0) #define GMAC_RXIPV4_GOOD_PACKETS 0x0810 #define GMAC_RXIPV4_HEADER_ERROR_PACKETS 0x0814 #define GMAC_RXIPV6_GOOD_PACKETS 0x0824 @@ -159,6 +450,26 @@ #define GMAC_RXTCP_ERROR_OCTETS 0x087C #define GMAC_RXICMP_ERROR_OCTETS 0x0884 #define GMAC_MAC_TIMESTAMP_CONTROL 0x0B00 +#define GMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEM (1U << 28) +#define GMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM (1U << 24) +#define GMAC_MAC_TIMESTAMP_CONTROL_ESTI (1U << 20) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR (1U << 18) +#define GMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT 16 +#define GMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK (3U << GMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA (1U << 15) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA (1U << 14) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA (1U << 13) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA (1U << 12) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSIPENA (1U << 11) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA (1U << 10) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR (1U << 9) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSENALL (1U << 8) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSADDREG (1U << 5) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSTRIG (1U << 4) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSUPDT (1U << 3) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSINIT (1U << 2) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT (1U << 1) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSENA (1U << 0) #define GMAC_MAC_SUB_SECOND_INCREMENT 0x0B04 #define GMAC_MAC_SYSTEM_TIME_SECS 0x0B08 #define GMAC_MAC_SYSTEM_TIME_NS 0x0B0C @@ -177,45 +488,173 @@ #define GMAC_MAC_TS_EGRESS_LATENCY 0x0B6C #define GMAC_MAC_PPS_CONTROL 0x0B70 #define GMAC_MTL_DBG_CTL 0x0C08 +#define GMAC_MTL_DBG_CTL_STSIE (1U << 15) +#define GMAC_MTL_DBG_CTL_PKTIE (1U << 14) +#define GMAC_MTL_DBG_CTL_FIFOSEL_SHIFT 12 +#define GMAC_MTL_DBG_CTL_FIFOSEL_MASK (3U << GMAC_MTL_DBG_CTL_FIFOSEL_SHIFT) +#define GMAC_MTL_DBG_CTL_FIFOSEL_TX_FIFO (0U << GMAC_MTL_DBG_CTL_FIFOSEL_SHIFT) +#define GMAC_MTL_DBG_CTL_FIFOSEL_TX_STATUS (1U << GMAC_MTL_DBG_CTL_FIFOSEL_SHIFT) +#define GMAC_MTL_DBG_CTL_FIFOSEL_TSO_FIFO (2U << GMAC_MTL_DBG_CTL_FIFOSEL_SHIFT) +#define GMAC_MTL_DBG_CTL_FIFOSEL_RX_FIFO (3U << GMAC_MTL_DBG_CTL_FIFOSEL_SHIFT) +#define GMAC_MTL_DBG_CTL_FIFOWREN (1U << 11) +#define GMAC_MTL_DBG_CTL_FIFORDEN (1U << 10) +#define GMAC_MTL_DBG_CTL_RSTSEL (1U << 9) +#define GMAC_MTL_DBG_CTL_RSTALL (1U << 8) +#define GMAC_MTL_DBG_CTL_PKTSTATE_SHIFT 5 +#define GMAC_MTL_DBG_CTL_PKTSTATE_MASK (3U << GMAC_MTL_DBG_CTL_PKTSTATE_SHIFT) +#define GMAC_MTL_DBG_CTL_PKTSTATE_PACKET_DATA (0U << GMAC_MTL_DBG_CTL_PKTSTATE_SHIFT) +#define GMAC_MTL_DBG_CTL_PKTSTATE_CONTROL_WORD (1U << GMAC_MTL_DBG_CTL_PKTSTATE_SHIFT) +#define GMAC_MTL_DBG_CTL_PKTSTATE_NORMAL_STATUS (1U << GMAC_MTL_DBG_CTL_PKTSTATE_SHIFT) +#define GMAC_MTL_DBG_CTL_PKTSTATE_SOP_DATA (2U << GMAC_MTL_DBG_CTL_PKTSTATE_SHIFT) +#define GMAC_MTL_DBG_CTL_PKTSTATE_LAST_STATUS (2U << GMAC_MTL_DBG_CTL_PKTSTATE_SHIFT) +#define GMAC_MTL_DBG_CTL_PKTSTATE_EOP (3U << GMAC_MTL_DBG_CTL_PKTSTATE_SHIFT) +#define GMAC_MTL_DBG_CTL_BYTEEN_SHIFT 2 +#define GMAC_MTL_DBG_CTL_BYTEEN_MASK (3U << GMAC_MTL_DBG_CTL_BYTEEN_SHIFT) +#define GMAC_MTL_DBG_CTL_BYTEEN_B0VALID (0U << GMAC_MTL_DBG_CTL_BYTEEN_SHIFT) +#define GMAC_MTL_DBG_CTL_BYTEEN_B01VALID (1U << GMAC_MTL_DBG_CTL_BYTEEN_SHIFT) +#define GMAC_MTL_DBG_CTL_BYTEEN_B012VALID (2U << GMAC_MTL_DBG_CTL_BYTEEN_SHIFT) +#define GMAC_MTL_DBG_CTL_BYTEEN_B0123VALID (3U << GMAC_MTL_DBG_CTL_BYTEEN_SHIFT) +#define GMAC_MTL_DBG_CTL_DBGMOD (1U << 1) +#define GMAC_MTL_DBG_CTL_FDBGEN (1U << 0) #define GMAC_MTL_DBG_STS 0x0C0C +#define GMAC_MTL_DBG_STS_LOCR (1U << 15) +#define GMAC_MTL_DBG_STS_STSI (1U << 9) +#define GMAC_MTL_DBG_STS_PKTI (1U << 8) +#define GMAC_MTL_DBG_STS_BYTEEN_SHIFT 3 +#define GMAC_MTL_DBG_STS_BYTEEN_MASK (3U << GMAC_MTL_DBG_STS_BYTEEN_SHIFT) +#define GMAC_MTL_DBG_STS_BYTEEN_B0VALID (0U << GMAC_MTL_DBG_STS_BYTEEN_SHIFT) +#define GMAC_MTL_DBG_STS_BYTEEN_B01VALID (1U << GMAC_MTL_DBG_STS_BYTEEN_SHIFT) +#define GMAC_MTL_DBG_STS_BYTEEN_B012VALID (3U << GMAC_MTL_DBG_STS_BYTEEN_SHIFT) +#define GMAC_MTL_DBG_STS_BYTEEN_B0123VALID (3U << GMAC_MTL_DBG_STS_BYTEEN_SHIFT) +#define GMAC_MTL_DBG_STS_PKTSTATE_SHIFT 1 +#define GMAC_MTL_DBG_STS_PKTSTATE_MASK (3U << GMAC_MTL_DBG_STS_PKTSTATE_SHIFT) +#define GMAC_MTL_DBG_STS_PKTSTATE_PACKET_DATA (0U << GMAC_MTL_DBG_STS_PKTSTATE_SHIFT) +#define GMAC_MTL_DBG_STS_PKTSTATE_CONTROL_WORD (1U << GMAC_MTL_DBG_STS_PKTSTATE_SHIFT) +#define GMAC_MTL_DBG_STS_PKTSTATE_NORMAL_STATUS (1U << GMAC_MTL_DBG_STS_PKTSTATE_SHIFT) +#define GMAC_MTL_DBG_STS_PKTSTATE_SOP_DATA (2U << GMAC_MTL_DBG_STS_PKTSTATE_SHIFT) +#define GMAC_MTL_DBG_STS_PKTSTATE_LAST_STATUS (2U << GMAC_MTL_DBG_STS_PKTSTATE_SHIFT) +#define GMAC_MTL_DBG_STS_PKTSTATE_EOP (3U << GMAC_MTL_DBG_STS_PKTSTATE_SHIFT) +#define GMAC_MTL_DBG_STS_FIFOBUSY (1U << 0) #define GMAC_MTL_FIFO_DEBUG_DATA 0x0C10 #define GMAC_MTL_INTERRUPT_STATUS 0x0C20 #define GMAC_MTL_INTERRUPT_STATUS_DBGIS (1U << 17) #define GMAC_MTL_INTERRUPT_STATUS_Q0IS (1U << 0) #define GMAC_MTL_TXQ0_OPERATION_MODE 0x0D00 +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT 6 +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK (7U << GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_32B (0U << GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_64B (1U << GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_96B (2U << GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_128B (3U << GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_192B (4U << GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_256B (5U << GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_384B (6U << GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_512B (7U << GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2 #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK (0x3U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT) #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_EN (2U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT) #define GMAC_MTL_TXQ0_OPERATION_MODE_TSF (1U << 1) #define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ (1U << 0) #define GMAC_MTL_TXQ0_UNDERFLOW 0x0D04 +#define GMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF (1U << 11) +#define GMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK (0x3FFU << 0) #define GMAC_MTL_TXQ0_DEBUG 0x0D08 +#define GMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT 20 +#define GMAC_MTL_TXQ0_DEBUG_STXSTSF_MASK (7U << GMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT) +#define GMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT 16 +#define GMAC_MTL_TXQ0_DEBUG_PTXQ_MASK (7U << GMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT) +#define GMAC_MTL_TXQ0_DEBUG_TXSTSFSTS (1U << 5) +#define GMAC_MTL_TXQ0_DEBUG_TXQSTS (1U << 4) +#define GMAC_MTL_TXQ0_DEBUG_TWCSTS (1U << 3) +#define GMAC_MTL_TXQ0_DEBUG_TRCSCS_SHIFT 1 +#define GMAC_MTL_TXQ0_DEBUG_TRCSCS_MASK (3U << GMAC_MTL_TXQ0_DEBUG_TRCSCS_SHIFT) +#define GMAC_MTL_TXQ0_DEBUG_TRCSCS_IDLE (0U << GMAC_MTL_TXQ0_DEBUG_TRCSCS_SHIFT) +#define GMAC_MTL_TXQ0_DEBUG_TRCSCS_READ (1U << GMAC_MTL_TXQ0_DEBUG_TRCSCS_SHIFT) +#define GMAC_MTL_TXQ0_DEBUG_TRCSCS_WAIT (2U << GMAC_MTL_TXQ0_DEBUG_TRCSCS_SHIFT) +#define GMAC_MTL_TXQ0_DEBUG_TRCSCS_FLUSH (3U << GMAC_MTL_TXQ0_DEBUG_TRCSCS_SHIFT) +#define GMAC_MTL_TXQ0_DEBUG_TXQPAUSED (1U << 0) #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS 0x0D2C #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE (1U << 24) #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS (1U << 16) #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE (1U << 8) #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS (1U << 0) #define GMAC_MTL_RXQ0_OPERATION_MODE 0x0D30 +#define GMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14 +#define GMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK (0x3FU << GMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) +#define GMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8 +#define GMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK (0x3FU << GMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT) +#define GMAC_MTL_RXQ0_OPERATION_MODE_EHFC (1U << 7) +#define GMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF (1U << 6) #define GMAC_MTL_RXQ0_OPERATION_MODE_RSF (1U << 5) #define GMAC_MTL_RXQ0_OPERATION_MODE_FEP (1U << 4) #define GMAC_MTL_RXQ0_OPERATION_MODE_FUP (1U << 3) +#define GMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK (3U << 0) #define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT 0x0D34 +#define GMAC_MTL_RXQ0_MISS_PKC_OVF_CNT_MISCNTOVF (1U << 27) +#define GMAC_MTL_RXQ0_MISS_PKC_OVF_CNT_MISPKTCNT_SHIFT 16 +#define GMAC_MTL_RXQ0_MISS_PKC_OVF_CNT_MISPKTCNT_MASK (0x7FFU << GMAC_MTL_RXQ0_MISS_PKC_OVF_CNT_MISPKTCNT_SHIFT) +#define GMAC_MTL_RXQ0_MISS_PKC_OVF_CNT_OVFCNTOVF (1U << 11) +#define GMAC_MTL_RXQ0_MISS_PKC_OVF_CNT_OVFPKTCNT (0x7FFU << 0) #define GMAC_MTL_RXQ0_DEBUG 0x0D38 +#define GMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16 +#define GMAC_MTL_RXQ0_DEBUG_PRXQ_MASK (0xFU << GMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT) +#define GMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4 +#define GMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK (3U << GMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) +#define GMAC_MTL_RXQ0_DEBUG_RXQSTS_EMPTY (0U << GMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) +#define GMAC_MTL_RXQ0_DEBUG_RXQSTS_LOW (1U << GMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) +#define GMAC_MTL_RXQ0_DEBUG_RXQSTS_HIGH (2U << GMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) +#define GMAC_MTL_RXQ0_DEBUG_RXQSTS_FULL (3U << GMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) +#define GMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT 1 +#define GMAC_MTL_RXQ0_DEBUG_RRCSTS_MASK (3U << GMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT) +#define GMAC_MTL_RXQ0_DEBUG_RRCSTS_IDLE (0U << GMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT) +#define GMAC_MTL_RXQ0_DEBUG_RRCSTS_RDATA (1U << GMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT) +#define GMAC_MTL_RXQ0_DEBUG_RRCSTS_RSTATUS (2U << GMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT) +#define GMAC_MTL_RXQ0_DEBUG_RRCSTS_FLUSH (3U << GMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT) +#define GMAC_MTL_RXQ0_DEBUG_RWCSTS (1U << 0) #define GMAC_DMA_MODE 0x1000 +#define GMAC_DMA_MODE_INTM_SHIFT 16 +#define GMAC_DMA_MODE_INTM_MASK (3U << GMAC_DMA_MODE_INTM_SHIFT) +#define GMAC_DMA_MODE_DSPW (1U << 8) #define GMAC_DMA_MODE_SWR (1U << 0) #define GMAC_DMA_SYSBUS_MODE 0x1004 +#define GMAC_DMA_SYSBUS_MODE_EN_LPI (1U << 31) +#define GMAC_DMA_SYSBUS_MODE_LPI_XIT_PKT (1U << 30) #define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT 24 #define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0x3U << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT) #define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16 #define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0x7U << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) #define GMAC_DMA_SYSBUS_MODE_MB (1U << 14) +#define GMAC_DMA_SYSBUS_MODE_AAL (1U << 12) #define GMAC_DMA_SYSBUS_MODE_EAME (1U << 11) +#define GMAC_DMA_SYSBUS_MODE_AALE (1U << 10) #define GMAC_DMA_SYSBUS_MODE_BLEN16 (1U << 3) #define GMAC_DMA_SYSBUS_MODE_BLEN8 (1U << 2) #define GMAC_DMA_SYSBUS_MODE_BLEN4 (1U << 1) #define GMAC_DMA_SYSBUS_MODE_FB (1U << 0) #define GMAC_DMA_INTERRUPT_STATUS 0x1008 +#define GMAC_DMA_INTERRUPT_STATUS_MACIS (1U << 17) +#define GMAC_DMA_INTERRUPT_STATUS_MTLIS (1U << 16) +#define GMAC_DMA_INTERRUPT_STATUS_DC0IS (1U << 0) #define GMAC_DMA_DEBUG_STATUS0 0x100C +#define GMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT 12 +#define GMAC_DMA_DEBUG_STATUS0_TPS0_MASK (0xFU << GMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) +#define GMAC_DMA_DEBUG_STATUS0_TPS0_STOPPED (0U << GMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) +#define GMAC_DMA_DEBUG_STATUS0_TPS0_FETCH_TX (1U << GMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) +#define GMAC_DMA_DEBUG_STATUS0_TPS0_WAIT_STATUS (2U << GMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) +#define GMAC_DMA_DEBUG_STATUS0_TPS0_READ_DATA (3U << GMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) +#define GMAC_DMA_DEBUG_STATUS0_TPS0_TX_WRITE (4U << GMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) +#define GMAC_DMA_DEBUG_STATUS0_TPS0_SUSPENDED (6U << GMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) +#define GMAC_DMA_DEBUG_STATUS0_TPS0_CLOSE_TX (7U << GMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) +#define GMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT 8 +#define GMAC_DMA_DEBUG_STATUS0_RPS0_MASK (0xFU << GMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) +#define GMAC_DMA_DEBUG_STATUS0_RPS0_STOPPED (0U << GMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) +#define GMAC_DMA_DEBUG_STATUS0_RPS0_FETCH_RX (1U << GMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) +#define GMAC_DMA_DEBUG_STATUS0_RPS0_WAIT_RX (3U << GMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) +#define GMAC_DMA_DEBUG_STATUS0_RPS0_SUSPENDED (4U << GMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) +#define GMAC_DMA_DEBUG_STATUS0_RPS0_CLOSE_RX (6U << GMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) +#define GMAC_DMA_DEBUG_STATUS0_RPS0_XFER_RX (7U << GMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) +#define GMAC_DMA_DEBUG_STATUS0_AXRHSTS (1U << 1) +#define GMAC_DMA_DEBUG_STATUS0_AXWHSTS (1U << 0) #define GMAC_AXI_LPI_ENTRY_INTERVAL 0x1040 #define GMAC_RWK_FILTERn_BYTE_MASK(n) (0x10C0 + 0x4 * (n)) #define GMAC_RWK_FILTER01_CRC 0x10D0