Re: Orange Pi 6 Plus works (15.1-RELEASE)

On June 30, 2026 12:16:10 AM GMT+03:00, Kevin Day <kevin@your=2Eorg> wrote=
:
>The Orange Pi 6 Plus SBC works fine out of the box for the most part=2E 1=
2 arm cores (8 fast, 4 slower), 16/32/64GB of ram, Dual 5G ethernet, dual N=
VME slots, etc=2E
>
>It's a UEFI based system that just booted the memstick image okay and ins=
talled=2E I have not tested anything with the GPU or NPU, and the if_rge dr=
iver isn't in GENERIC on arm64 so I had to add that=2E The only issue is th=
at it's got CPU cores that are not all the same, and the scheduler doesn't =
seem to understand that:
>
>CPU  0: ARM Cortex-A720 r0p1 affinity: 10  0
>                   Cache Type =3D <IDC,64 byte CWG,64 byte ERG,64 byte D-=
cacheline,PIPT I-cache,64 byte I-cacheline,0x400000000>
> Instruction Set Attributes 0 =3D <TLBI-OSR,CondM-8=2E5,FHM,DP,SM4,SM3,SH=
A3,RDM,Atomic,CRC32,SHA2+SHA512,SHA1,AES+PMULL>
> Instruction Set Attributes 1 =3D <XS,I8MM,DGH,BF16,PredInv v8=2E5,SB,FRI=
NTTS,RCPC-8=2E4,FCMA,JSCVT,DCCVADP>
> Instruction Set Attributes 2 =3D <PAC_frac,APA3 FPAC+Combined,GPA3,WFxT>
>         Processor Features 0 =3D <CSV3,CSV2_2,PSTATE=2EDIT,AMUv1,MPAM,SE=
L2,SVE,RAS v8=2E4,GIC 4=2E1,AdvSIMD+HP,FP+HP,EL3,EL2,EL1,EL0>
>         Processor Features 1 =3D <MTE_frac,MPAM p1,MTE3,PSTATE=2ESSBS MS=
R,BTI>
>         Processor Features 2 =3D <>
>      Memory Model Features 0 =3D <ECV POFF,FGT v8=2E6,S2 TGran4,S2 TGran=
64,S2 TGran16,TGran4,TGran64,TGran16,SNSMem,BigEnd,16bit ASID,1TB PA>
>      Memory Model Features 1 =3D <ECBHB,nTLBPA,AFP,HCX,XNX,EPAN,LO,HPD+T=
TPBHA,VH,16bit VMID,HAF+DS>
>      Memory Model Features 2 =3D <E0PD,EVT-8=2E5,BBM level 2,TTL,FWB,IDS=
,AT,ST,64bit CCIDX,48bit VA,IESB,UAO,CnP>
>      Memory Model Features 3 =3D <>
>      Memory Model Features 4 =3D <>
>             Debug Features 0 =3D <HPMN0,MTPMU res0,TraceBuffer,Trace v8=
=2E4,SPEv1p2,2 CTX BKPTs,4 Watchpoints,6 Breakpoints,PMUv3p7,Trace,Debugv8p=
4>
>             Debug Features 1 =3D <>
>         Auxiliary Features 0 =3D <>
>         Auxiliary Features 1 =3D <>
>               SVE Features 0 =3D <I8MM,SM4,SHA3,BF16,BitPerm,AES+PMULL,S=
VE2>
>AArch32 Instruction Set Attributes 5 =3D <>
>AArch32 Media and VFP Features 0 =3D <>
>AArch32 Media and VFP Features 1 =3D <>
>CPU  1: ARM Cortex-A720 r0p1 affinity: 11  0
>CPU  2: ARM Cortex-A520 r0p1 affinity:  0  0
>      Memory Model Features 1 =3D <ECBHB,nTLBPA,AFP,HCX,XNX,SpecSEI,EPAN,=
LO,HPD+TTPBHA,VH,16bit VMID,HAF+DS>
>             Debug Features 0 =3D <HPMN0,MTPMU res0,TraceBuffer,Trace v8=
=2E4,2 CTX BKPTs,4 Watchpoints,6 Breakpoints,PMUv3p7,Trace,Debugv8p4>
>CPU  3: ARM Cortex-A520 r0p1 affinity:  1  0
>CPU  4: ARM Cortex-A520 r0p1 affinity:  2  0
>CPU  5: ARM Cortex-A520 r0p1 affinity:  3  0
>CPU  6: ARM Cortex-A720 r0p1 affinity:  4  0
>      Memory Model Features 1 =3D <ECBHB,nTLBPA,AFP,HCX,XNX,EPAN,LO,HPD+T=
TPBHA,VH,16bit VMID,HAF+DS>
>             Debug Features 0 =3D <HPMN0,MTPMU res0,TraceBuffer,Trace v8=
=2E4,SPEv1p2,2 CTX BKPTs,4 Watchpoints,6 Breakpoints,PMUv3p7,Trace,Debugv8p=
4>
>CPU  7: ARM Cortex-A720 r0p1 affinity:  5  0
>CPU  8: ARM Cortex-A720 r0p1 affinity:  6  0
>CPU  9: ARM Cortex-A720 r0p1 affinity:  7  0
>CPU 10: ARM Cortex-A720 r0p1 affinity:  8  0
>CPU 11: ARM Cortex-A720 r0p1 affinity:  9  0
>
>0-1,6-11 are fast, and 2-5 are slow=2E However, it seems like the schedul=
er is just randomly picking a core, so performance varies wildly depending =
on which one you hit=2E
>
>kern=2Esched=2Etopology_spec: <groups>
> <group level=3D"1" cache-level=3D"3">
>  <cpu count=3D"12" mask=3D"fff,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0">0, 1, 2, 3=
, 4, 5, 6, 7, 8, 9, 10, 11</cpu>
> </group>
></groups>
>
>
>Is there an easy fix for this? Linux gets it right, but I'm really unfami=
liar with the low level of arm board support to understand how/where it's l=
earning the topology=2E
>
>-- Kevin
>
>

i'm surprised it works at all

iirc, no multiple speed cpu systems have support in fbsd so far, i haven't=
 even heard it being planned, so booting current is not likely to help eith=
er

the more hw experienced guys(/gals?) can add additional info here or corre=
ct me or add any roadmaps