git: 5b795f7f0931 - main - graphics/nvidia-texture-tools: fix aarch64 and powerpc64* builds

The branch main has been updated by pkubaj:

URL: https://cgit.FreeBSD.org/ports/commit/?id=5b795f7f0931bd3967b65ff08703df66c6387786

commit 5b795f7f0931bd3967b65ff08703df66c6387786
Author:     Piotr Kubaj <[email protected]>
AuthorDate: 2026-08-06 09:58:31 +0000
Commit:     Piotr Kubaj <[email protected]>
CommitDate: 2026-08-06 13:14:43 +0000

    graphics/nvidia-texture-tools: fix aarch64 and powerpc64* builds
    
    Some of the code assumed amd64 / i386 and included SSE headers.
    icbc.h was plainly wrong and contained straight typos, probably never
    built previously on powerpc* hardware.
---
 graphics/nvidia-texture-tools/Makefile             |  1 -
 ...patch-extern_CMP__Core_source_cmp__math__vec4.h | 25 ++++++++
 .../files/patch-src_nvcore_Debug.cpp               | 15 +++++
 .../files/patch-src_nvcore_Debug.h                 | 11 ++++
 .../files/patch-src_nvtt_icbc.h                    | 66 ++++++++++++++++++++++
 5 files changed, 117 insertions(+), 1 deletion(-)

diff --git a/graphics/nvidia-texture-tools/Makefile b/graphics/nvidia-texture-tools/Makefile
index cc86f9665a1f..cc806d3d0b57 100644
--- a/graphics/nvidia-texture-tools/Makefile
+++ b/graphics/nvidia-texture-tools/Makefile
@@ -10,7 +10,6 @@ LICENSE=	MIT
 LICENSE_FILE=	${WRKSRC}/LICENSE
 
 ONLY_FOR_ARCHS=	i386 amd64 powerpc powerpc64 armv6 aarch64 powerpc64le # see src/nvcore/nvcore.h
-BROKEN_aarch64=	error: use of undeclared identifier '__builtin_ia32_emms'
 
 USES=		cmake compiler:c++11-lang
 CMAKE_ON=	NVTT_SHARED \
diff --git a/graphics/nvidia-texture-tools/files/patch-extern_CMP__Core_source_cmp__math__vec4.h b/graphics/nvidia-texture-tools/files/patch-extern_CMP__Core_source_cmp__math__vec4.h
new file mode 100644
index 000000000000..5ac0334928b4
--- /dev/null
+++ b/graphics/nvidia-texture-tools/files/patch-extern_CMP__Core_source_cmp__math__vec4.h
@@ -0,0 +1,25 @@
+--- extern/CMP_Core/source/cmp_math_vec4.h.orig	2020-08-24 06:27:21 UTC
++++ extern/CMP_Core/source/cmp_math_vec4.h
+@@ -322,10 +322,12 @@ class Vec4 (public)
+ };
+ 
+ #include <stdio.h>
+-#include "xmmintrin.h"
+ #include <math.h>
+ #include <float.h> 
+ 
++#if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
++#include "xmmintrin.h"
++
+ // SSE Vec4
+ #ifdef _LINUX
+ class CMP_SSEVec4f
+@@ -419,6 +421,8 @@ class   __declspec(align(16)) CMP_SSEVec4f (public)
+     };
+ 
+ };
++
++#endif
+ 
+ typedef Vec4<float>             CMP_Vec4f;
+ typedef Vec4<double>            CMP_Vec4d;
diff --git a/graphics/nvidia-texture-tools/files/patch-src_nvcore_Debug.cpp b/graphics/nvidia-texture-tools/files/patch-src_nvcore_Debug.cpp
new file mode 100644
index 000000000000..03bc35017897
--- /dev/null
+++ b/graphics/nvidia-texture-tools/files/patch-src_nvcore_Debug.cpp
@@ -0,0 +1,15 @@
+--- src/nvcore/Debug.cpp.orig	2020-08-24 06:27:21 UTC
++++ src/nvcore/Debug.cpp
+@@ -628,6 +628,12 @@ namespace 
+ #  elif NV_CPU_X86
+         ucontext_t * ucp = (ucontext_t *)secret;
+         return (void *)ucp->uc_mcontext.mc_eip;
++#  elif NV_CPU_PPC
++        ucontext_t * ucp = (ucontext_t *)secret;
++        return (void *)ucp->uc_mcontext.mc_srr0;
++#  elif NV_CPU_ARM_64
++        ucontext_t * ucp = (ucontext_t *)secret;
++        return (void *)ucp->uc_mcontext.mc_gpregs.gp_elr;
+ #    else
+ #      error "Unknown CPU"
+ #    endif
diff --git a/graphics/nvidia-texture-tools/files/patch-src_nvcore_Debug.h b/graphics/nvidia-texture-tools/files/patch-src_nvcore_Debug.h
new file mode 100644
index 000000000000..652605757a48
--- /dev/null
+++ b/graphics/nvidia-texture-tools/files/patch-src_nvcore_Debug.h
@@ -0,0 +1,11 @@
+--- src/nvcore/Debug.h.orig	2020-08-24 06:27:21 UTC
++++ src/nvcore/Debug.h
+@@ -166,7 +166,7 @@ namespace nv
+ namespace nv
+ {
+     inline bool isValidPtr(const void * ptr) {
+-    #if NV_CPU_X86_64 || POSH_CPU_PPC64 || NV_CPU_AARCH64
++    #if NV_CPU_X86_64 || POSH_CPU_PPC64 || NV_CPU_ARM_64
+         if (ptr == NULL) return true;
+         if (reinterpret_cast<uint64>(ptr) < 0x10000ULL) return false;
+         if (reinterpret_cast<uint64>(ptr) >= 0x000007FFFFFEFFFFULL) return false;
diff --git a/graphics/nvidia-texture-tools/files/patch-src_nvtt_icbc.h b/graphics/nvidia-texture-tools/files/patch-src_nvtt_icbc.h
new file mode 100644
index 000000000000..5959f1c8e852
--- /dev/null
+++ b/graphics/nvidia-texture-tools/files/patch-src_nvtt_icbc.h
@@ -0,0 +1,66 @@
+--- src/nvtt/icbc.h.orig	2020-08-24 06:27:21 UTC
++++ src/nvtt/icbc.h
+@@ -1195,7 +1195,7 @@ union VFloat {
+ constexpr int VEC_SIZE = 4;
+ 
+ union VFloat {
+-    vectro float v;
++    vector float v;
+     float e[4];
+     VFloat() {}
+     VFloat(vector float v) : v(v) {}
+@@ -1221,7 +1221,11 @@ ICBC_FORCEINLINE VFloat vload(const float * ptr) {
+ }
+ 
+ ICBC_FORCEINLINE VFloat vload(const float * ptr) {
+-    return vec_ld(ptr)
++#if defined(__VSX__)
++    return vec_xl(0, ptr);
++#else
++    return vec_ld(0, ptr);
++#endif
+ }
+ 
+ ICBC_FORCEINLINE VFloat operator+(VFloat a, VFloat b) {
+@@ -1245,7 +1249,7 @@ ICBC_FORCEINLINE VFloat vrcp(VFloat a) {
+     vector float diff = vec_nmsub( estimate, v.vec, vec_splats( 1.0f ) );
+     return vec_madd(diff, estimate, estimate );
+ #else
+-    return vec_div(vec_splats(1),a);
++    return vec_div(vec_splats(1.0f), a);
+ #endif
+ }
+ 
+@@ -1276,7 +1280,7 @@ ICBC_FORCEINLINE VFloat lane_id() {
+ }
+ 
+ ICBC_FORCEINLINE VFloat lane_id() {
+-    return (VFloat){ 0, 1, 2, 3 };
++    return (vector float){ 0, 1, 2, 3 };
+ }
+ 
+ ICBC_FORCEINLINE VMask operator> (VFloat A, VFloat B) { return { vec_cmpgt(A, B) }; }
+@@ -1291,6 +1295,23 @@ ICBC_FORCEINLINE VFloat vselect(VMask mask, VFloat a, 
+ // mask ? b : a
+ ICBC_FORCEINLINE VFloat vselect(VMask mask, VFloat a, VFloat b) {
+     return vec_sel(a, b, mask);
++}
++
++ICBC_FORCEINLINE bool all(VMask mask) {
++    return vec_all_ne(mask.v, vec_splats(0u));
++}
++
++ICBC_FORCEINLINE bool any(VMask mask) {
++    return vec_any_ne(mask.v, vec_splats(0u));
++}
++
++ICBC_FORCEINLINE uint mask(VMask mask) {
++    const vector unsigned int movemask = { 1, 2, 4, 8 };
++    const vector unsigned int highbit = { 0x80000000, 0x80000000, 0x80000000, 0x80000000 };
++
++    vector unsigned int bits = vec_and(vec_cmpeq(vec_and(mask.v, highbit), highbit), movemask);
++
++    return bits[0] | bits[1] | bits[2] | bits[3];
+ }
+ 
+ ICBC_FORCEINLINE int reduce_min_index(VFloat v) {