git: 4d2f90f5a694 - main - riscv: Add support for the Svinval extension

The branch main has been updated by bnovkov:

URL: https://cgit.FreeBSD.org/src/commit/?id=4d2f90f5a694b89240c494c01a5c07e24131f6f0

commit 4d2f90f5a694b89240c494c01a5c07e24131f6f0
Author:     Bojan Novković <[email protected]>
AuthorDate: 2026-06-16 14:55:04 +0000
Commit:     Bojan Novković <[email protected]>
CommitDate: 2026-08-10 16:00:00 +0000

    riscv: Add support for the Svinval extension
    
    This change adds wrappers for the new fine-grained TLB invalidation
    instructions and extends the capability detection logic to include
    the Svinval extension, which is mandatory in the RVA23S64 profile.
    
    Event:  BSDCan 2026
    Differential Revision:  https://reviews.freebsd.org/D57623
    Reviewed by:    mhorne, markj
---
 sys/conf/kern.mk            |  2 +-
 sys/riscv/include/cpufunc.h | 28 ++++++++++++++++++++++++++++
 sys/riscv/include/md_var.h  |  1 +
 sys/riscv/riscv/identcpu.c  |  2 ++
 4 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/sys/conf/kern.mk b/sys/conf/kern.mk
index b87583db21c5..3c3442e63d31 100644
--- a/sys/conf/kern.mk
+++ b/sys/conf/kern.mk
@@ -166,7 +166,7 @@ INLINE_LIMIT?=	8000
 # code model as "medium" and "medany" respectively.
 #
 .if ${MACHINE_CPUARCH} == "riscv"
-CFLAGS+=	-march=rv64imafdch_zifencei
+CFLAGS+=	-march=rv64imafdch_zifencei_svinval
 CFLAGS+=	-mabi=lp64
 CFLAGS.clang+=	-mcmodel=medium
 CFLAGS.gcc+=	-mcmodel=medany
diff --git a/sys/riscv/include/cpufunc.h b/sys/riscv/include/cpufunc.h
index e7bfeeb0cf59..40b1d0b95451 100644
--- a/sys/riscv/include/cpufunc.h
+++ b/sys/riscv/include/cpufunc.h
@@ -126,6 +126,34 @@ hfence_gvma(void)
 	__asm __volatile("hfence.gvma" ::: "memory");
 }
 
+static __inline void
+sfence_inval_ir(void)
+{
+
+	__asm __volatile("sfence.inval.ir" ::: "memory");
+}
+
+static __inline void
+sfence_w_inval(void)
+{
+
+	__asm __volatile("sfence.w.inval" ::: "memory");
+}
+
+static __inline void
+sinval_vma_page(uintptr_t addr)
+{
+
+	__asm __volatile("sinval.vma %0, zero" :: "r" (addr) : "memory");
+}
+
+static __inline void
+sinval_vma_page_asid(uintptr_t addr, uint64_t asid)
+{
+
+	__asm __volatile("sinval.vma %0, %1" :: "r" (addr), "r" (asid) : "memory");
+}
+
 #define	rdcycle()			csr_read64(cycle)
 #define	rdtime()			csr_read64(time)
 #define	rdinstret()			csr_read64(instret)
diff --git a/sys/riscv/include/md_var.h b/sys/riscv/include/md_var.h
index 5f921ed500bf..b47ef2f49fd4 100644
--- a/sys/riscv/include/md_var.h
+++ b/sys/riscv/include/md_var.h
@@ -47,6 +47,7 @@ extern bool has_sstc;
 extern bool has_sscofpmf;
 extern bool has_svpbmt;
 extern bool has_vector;
+extern bool has_svinval;
 
 struct dumperinfo;
 struct minidumpstate;
diff --git a/sys/riscv/riscv/identcpu.c b/sys/riscv/riscv/identcpu.c
index 3b747576db48..ca1b2b9ae1af 100644
--- a/sys/riscv/riscv/identcpu.c
+++ b/sys/riscv/riscv/identcpu.c
@@ -79,6 +79,7 @@ bool has_vector;
 bool __read_frequently has_sstc;
 bool __read_frequently has_sscofpmf;
 bool has_svpbmt;
+bool has_svinval;
 
 /* Z-extensions support. */
 bool has_zicbom;
@@ -478,6 +479,7 @@ update_global_capabilities(u_int cpu, struct cpu_desc *desc)
 	UPDATE_CAP(has_sstc, (desc->smode_extensions & SV_SSTC) != 0);
 	UPDATE_CAP(has_sscofpmf, (desc->smode_extensions & SV_SSCOFPMF) != 0);
 	UPDATE_CAP(has_svpbmt, (desc->smode_extensions & SV_SVPBMT) != 0);
+	UPDATE_CAP(has_svinval, (desc->smode_extensions & SV_SVINVAL) != 0);
 
 	/* Z extension support. */
 	UPDATE_CAP(has_zicbom, (desc->z_extensions & Z_ZICBOM) != 0);