git: 6c41d1e26614 - main - libcxgb4: Use t4fw_interface.h from the cxgbe driver sources
John Baldwin <[email protected]>
| Newsgroups | gmane.os.freebsd.devel.cvs.src |
|---|---|
| Message-ID | <6a7e01d4.1faf5.60f277f8__7879.85353251628$1786642927$gmane$org@gitrepo.freebsd.org> |
The branch main has been updated by jhb: URL: https://cgit.FreeBSD.org/src/commit/?id=6c41d1e26614385c7dda03d62a62084d01a1741e commit 6c41d1e26614385c7dda03d62a62084d01a1741e Author: John Baldwin <[email protected]> AuthorDate: 2026-08-13 17:02:17 +0000 Commit: John Baldwin <[email protected]> CommitDate: 2026-08-13 17:02:17 +0000 libcxgb4: Use t4fw_interface.h from the cxgbe driver sources In Linux these are maintained in separate places so a separate copy is needed, but in FreeBSD take advantage of the shared tree to avoid having a duplicate copy that can be stale. Reviewed by: np Sponsored by: Chelsio Communications Differential Revision: https://reviews.freebsd.org/D58575 --- contrib/ofed/libcxgb4/qp.c | 6 +- contrib/ofed/libcxgb4/t4.h | 4 +- contrib/ofed/libcxgb4/t4fw_api.h | 3260 ----------------------------------- contrib/ofed/libcxgb4/t4fw_ri_api.h | 756 -------- lib/ofed/libcxgb4/Makefile | 1 + 5 files changed, 6 insertions(+), 4021 deletions(-) diff --git a/contrib/ofed/libcxgb4/qp.c b/contrib/ofed/libcxgb4/qp.c index bd2c38528643..351cf621b82d 100644 --- a/contrib/ofed/libcxgb4/qp.c +++ b/contrib/ofed/libcxgb4/qp.c @@ -166,10 +166,10 @@ static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe, return -EINVAL; if (wr->send_flags & IBV_SEND_SOLICITED) wqe->send.sendop_pkd = htobe32( - FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE)); + V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE)); else wqe->send.sendop_pkd = htobe32( - FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND)); + V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND)); wqe->send.stag_inv = 0; wqe->send.r3 = 0; wqe->send.r4 = 0; @@ -213,7 +213,7 @@ static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe, if (wr->num_sge > T4_MAX_SEND_SGE) return -EINVAL; - wqe->write.r2 = 0; + wqe->write.immd_data = 0; wqe->write.stag_sink = htobe32(wr->wr.rdma.rkey); wqe->write.to_sink = htobe64(wr->wr.rdma.remote_addr); if (wr->num_sge) { diff --git a/contrib/ofed/libcxgb4/t4.h b/contrib/ofed/libcxgb4/t4.h index 05984e87d569..ba7d578bf390 100644 --- a/contrib/ofed/libcxgb4/t4.h +++ b/contrib/ofed/libcxgb4/t4.h @@ -33,6 +33,7 @@ #include <assert.h> #include <errno.h> +#include <stdbool.h> #include <stddef.h> #include <stdint.h> #include <syslog.h> @@ -61,8 +62,7 @@ #include "t4_regs.h" #include "t4_chip_type.h" -#include "t4fw_api.h" -#include "t4fw_ri_api.h" +#include "t4fw_interface.h" #ifdef DEBUG #define DBGLOG(s) diff --git a/contrib/ofed/libcxgb4/t4fw_api.h b/contrib/ofed/libcxgb4/t4fw_api.h deleted file mode 100644 index 07698bb3034a..000000000000 --- a/contrib/ofed/libcxgb4/t4fw_api.h +++ /dev/null @@ -1,3260 +0,0 @@ -/* - * This file is part of the Chelsio T4 Ethernet driver for Linux. - * - * Copyright (c) 2009-2014 Chelsio Communications, Inc. All rights reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the - * OpenIB.org BSD license below: - * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * - Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * - * - Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#ifndef _T4FW_INTERFACE_H_ -#define _T4FW_INTERFACE_H_ - -#include <infiniband/types.h> - -enum fw_retval { - FW_SUCCESS = 0, /* completed successfully */ - FW_EPERM = 1, /* operation not permitted */ - FW_ENOENT = 2, /* no such file or directory */ - FW_EIO = 5, /* input/output error; hw bad */ - FW_ENOEXEC = 8, /* exec format error; inv microcode */ - FW_EAGAIN = 11, /* try again */ - FW_ENOMEM = 12, /* out of memory */ - FW_EFAULT = 14, /* bad address; fw bad */ - FW_EBUSY = 16, /* resource busy */ - FW_EEXIST = 17, /* file exists */ - FW_ENODEV = 19, /* no such device */ - FW_EINVAL = 22, /* invalid argument */ - FW_ENOSPC = 28, /* no space left on device */ - FW_ENOSYS = 38, /* functionality not implemented */ - FW_ENODATA = 61, /* no data available */ - FW_EPROTO = 71, /* protocol error */ - FW_EADDRINUSE = 98, /* address already in use */ - FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ - FW_ENETDOWN = 100, /* network is down */ - FW_ENETUNREACH = 101, /* network is unreachable */ - FW_ENOBUFS = 105, /* no buffer space available */ - FW_ETIMEDOUT = 110, /* timeout */ - FW_EINPROGRESS = 115, /* fw internal */ - FW_SCSI_ABORT_REQUESTED = 128, /* */ - FW_SCSI_ABORT_TIMEDOUT = 129, /* */ - FW_SCSI_ABORTED = 130, /* */ - FW_SCSI_CLOSE_REQUESTED = 131, /* */ - FW_ERR_LINK_DOWN = 132, /* */ - FW_RDEV_NOT_READY = 133, /* */ - FW_ERR_RDEV_LOST = 134, /* */ - FW_ERR_RDEV_LOGO = 135, /* */ - FW_FCOE_NO_XCHG = 136, /* */ - FW_SCSI_RSP_ERR = 137, /* */ - FW_ERR_RDEV_IMPL_LOGO = 138, /* */ - FW_SCSI_UNDER_FLOW_ERR = 139, /* */ - FW_SCSI_OVER_FLOW_ERR = 140, /* */ - FW_SCSI_DDP_ERR = 141, /* DDP error*/ - FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ -}; - -#define FW_T4VF_SGE_BASE_ADDR 0x0000 -#define FW_T4VF_MPS_BASE_ADDR 0x0100 -#define FW_T4VF_PL_BASE_ADDR 0x0200 -#define FW_T4VF_MBDATA_BASE_ADDR 0x0240 -#define FW_T4VF_CIM_BASE_ADDR 0x0300 - -enum fw_wr_opcodes { - FW_FILTER_WR = 0x02, - FW_ULPTX_WR = 0x04, - FW_TP_WR = 0x05, - FW_ETH_TX_PKT_WR = 0x08, - FW_OFLD_CONNECTION_WR = 0x2f, - FW_FLOWC_WR = 0x0a, - FW_OFLD_TX_DATA_WR = 0x0b, - FW_CMD_WR = 0x10, - FW_ETH_TX_PKT_VM_WR = 0x11, - FW_RI_RES_WR = 0x0c, - FW_RI_INIT_WR = 0x0d, - FW_RI_RDMA_WRITE_WR = 0x14, - FW_RI_SEND_WR = 0x15, - FW_RI_RDMA_READ_WR = 0x16, - FW_RI_RECV_WR = 0x17, - FW_RI_BIND_MW_WR = 0x18, - FW_RI_FR_NSMR_WR = 0x19, - FW_RI_INV_LSTAG_WR = 0x1a, - FW_ISCSI_TX_DATA_WR = 0x45, - FW_LASTC2E_WR = 0x70 -}; - -struct fw_wr_hdr { - __be32 hi; - __be32 lo; -}; - -/* work request opcode (hi) */ -#define FW_WR_OP_S 24 -#define FW_WR_OP_M 0xff -#define FW_WR_OP_V(x) ((x) << FW_WR_OP_S) -#define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M) - -/* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */ -#define FW_WR_ATOMIC_S 23 -#define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S) - -/* flush flag (hi) - firmware flushes flushable work request buffered - * in the flow context. - */ -#define FW_WR_FLUSH_S 22 -#define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S) - -/* completion flag (hi) - firmware generates a cpl_fw6_ack */ -#define FW_WR_COMPL_S 21 -#define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S) -#define FW_WR_COMPL_F FW_WR_COMPL_V(1U) - -/* work request immediate data length (hi) */ -#define FW_WR_IMMDLEN_S 0 -#define FW_WR_IMMDLEN_M 0xff -#define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S) - -/* egress queue status update to associated ingress queue entry (lo) */ -#define FW_WR_EQUIQ_S 31 -#define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S) -#define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U) - -/* egress queue status update to egress queue status entry (lo) */ -#define FW_WR_EQUEQ_S 30 -#define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S) -#define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U) - -/* flow context identifier (lo) */ -#define FW_WR_FLOWID_S 8 -#define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S) - -/* length in units of 16-bytes (lo) */ -#define FW_WR_LEN16_S 0 -#define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S) - -#define HW_TPL_FR_MT_PR_IV_P_FC 0X32B -#define HW_TPL_FR_MT_PR_OV_P_FC 0X327 - -/* filter wr reply code in cookie in CPL_SET_TCB_RPL */ -enum fw_filter_wr_cookie { - FW_FILTER_WR_SUCCESS, - FW_FILTER_WR_FLT_ADDED, - FW_FILTER_WR_FLT_DELETED, - FW_FILTER_WR_SMT_TBL_FULL, - FW_FILTER_WR_EINVAL, -}; - -struct fw_filter_wr { - __be32 op_pkd; - __be32 len16_pkd; - __be64 r3; - __be32 tid_to_iq; - __be32 del_filter_to_l2tix; - __be16 ethtype; - __be16 ethtypem; - __u8 frag_to_ovlan_vldm; - __u8 smac_sel; - __be16 rx_chan_rx_rpl_iq; - __be32 maci_to_matchtypem; - __u8 ptcl; - __u8 ptclm; - __u8 ttyp; - __u8 ttypm; - __be16 ivlan; - __be16 ivlanm; - __be16 ovlan; - __be16 ovlanm; - __u8 lip[16]; - __u8 lipm[16]; - __u8 fip[16]; - __u8 fipm[16]; - __be16 lp; - __be16 lpm; - __be16 fp; - __be16 fpm; - __be16 r7; - __u8 sma[6]; -}; - -#define FW_FILTER_WR_TID_S 12 -#define FW_FILTER_WR_TID_M 0xfffff -#define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S) -#define FW_FILTER_WR_TID_G(x) \ - (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M) - -#define FW_FILTER_WR_RQTYPE_S 11 -#define FW_FILTER_WR_RQTYPE_M 0x1 -#define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S) -#define FW_FILTER_WR_RQTYPE_G(x) \ - (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M) -#define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U) - -#define FW_FILTER_WR_NOREPLY_S 10 -#define FW_FILTER_WR_NOREPLY_M 0x1 -#define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S) -#define FW_FILTER_WR_NOREPLY_G(x) \ - (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M) -#define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U) - -#define FW_FILTER_WR_IQ_S 0 -#define FW_FILTER_WR_IQ_M 0x3ff -#define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S) -#define FW_FILTER_WR_IQ_G(x) \ - (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M) - -#define FW_FILTER_WR_DEL_FILTER_S 31 -#define FW_FILTER_WR_DEL_FILTER_M 0x1 -#define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S) -#define FW_FILTER_WR_DEL_FILTER_G(x) \ - (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M) -#define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U) - -#define FW_FILTER_WR_RPTTID_S 25 -#define FW_FILTER_WR_RPTTID_M 0x1 -#define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S) -#define FW_FILTER_WR_RPTTID_G(x) \ - (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M) -#define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U) - -#define FW_FILTER_WR_DROP_S 24 -#define FW_FILTER_WR_DROP_M 0x1 -#define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S) -#define FW_FILTER_WR_DROP_G(x) \ - (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M) -#define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U) - -#define FW_FILTER_WR_DIRSTEER_S 23 -#define FW_FILTER_WR_DIRSTEER_M 0x1 -#define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S) -#define FW_FILTER_WR_DIRSTEER_G(x) \ - (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M) -#define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U) - -#define FW_FILTER_WR_MASKHASH_S 22 -#define FW_FILTER_WR_MASKHASH_M 0x1 -#define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S) -#define FW_FILTER_WR_MASKHASH_G(x) \ - (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M) -#define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U) - -#define FW_FILTER_WR_DIRSTEERHASH_S 21 -#define FW_FILTER_WR_DIRSTEERHASH_M 0x1 -#define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S) -#define FW_FILTER_WR_DIRSTEERHASH_G(x) \ - (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M) -#define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U) - -#define FW_FILTER_WR_LPBK_S 20 -#define FW_FILTER_WR_LPBK_M 0x1 -#define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S) -#define FW_FILTER_WR_LPBK_G(x) \ - (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M) -#define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U) - -#define FW_FILTER_WR_DMAC_S 19 -#define FW_FILTER_WR_DMAC_M 0x1 -#define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S) -#define FW_FILTER_WR_DMAC_G(x) \ - (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M) -#define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U) - -#define FW_FILTER_WR_SMAC_S 18 -#define FW_FILTER_WR_SMAC_M 0x1 -#define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S) -#define FW_FILTER_WR_SMAC_G(x) \ - (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M) -#define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U) - -#define FW_FILTER_WR_INSVLAN_S 17 -#define FW_FILTER_WR_INSVLAN_M 0x1 -#define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S) -#define FW_FILTER_WR_INSVLAN_G(x) \ - (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M) -#define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U) - -#define FW_FILTER_WR_RMVLAN_S 16 -#define FW_FILTER_WR_RMVLAN_M 0x1 -#define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S) -#define FW_FILTER_WR_RMVLAN_G(x) \ - (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M) -#define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U) - -#define FW_FILTER_WR_HITCNTS_S 15 -#define FW_FILTER_WR_HITCNTS_M 0x1 -#define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S) -#define FW_FILTER_WR_HITCNTS_G(x) \ - (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M) -#define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U) - -#define FW_FILTER_WR_TXCHAN_S 13 -#define FW_FILTER_WR_TXCHAN_M 0x3 -#define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S) -#define FW_FILTER_WR_TXCHAN_G(x) \ - (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M) - -#define FW_FILTER_WR_PRIO_S 12 -#define FW_FILTER_WR_PRIO_M 0x1 -#define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S) -#define FW_FILTER_WR_PRIO_G(x) \ - (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M) -#define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U) - -#define FW_FILTER_WR_L2TIX_S 0 -#define FW_FILTER_WR_L2TIX_M 0xfff -#define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S) -#define FW_FILTER_WR_L2TIX_G(x) \ - (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M) - -#define FW_FILTER_WR_FRAG_S 7 -#define FW_FILTER_WR_FRAG_M 0x1 -#define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S) -#define FW_FILTER_WR_FRAG_G(x) \ - (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M) -#define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U) - -#define FW_FILTER_WR_FRAGM_S 6 -#define FW_FILTER_WR_FRAGM_M 0x1 -#define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S) -#define FW_FILTER_WR_FRAGM_G(x) \ - (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M) -#define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U) - -#define FW_FILTER_WR_IVLAN_VLD_S 5 -#define FW_FILTER_WR_IVLAN_VLD_M 0x1 -#define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S) -#define FW_FILTER_WR_IVLAN_VLD_G(x) \ - (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M) -#define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U) - -#define FW_FILTER_WR_OVLAN_VLD_S 4 -#define FW_FILTER_WR_OVLAN_VLD_M 0x1 -#define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S) -#define FW_FILTER_WR_OVLAN_VLD_G(x) \ - (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M) -#define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U) - -#define FW_FILTER_WR_IVLAN_VLDM_S 3 -#define FW_FILTER_WR_IVLAN_VLDM_M 0x1 -#define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S) -#define FW_FILTER_WR_IVLAN_VLDM_G(x) \ - (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M) -#define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U) - -#define FW_FILTER_WR_OVLAN_VLDM_S 2 -#define FW_FILTER_WR_OVLAN_VLDM_M 0x1 -#define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S) -#define FW_FILTER_WR_OVLAN_VLDM_G(x) \ - (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M) -#define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U) - -#define FW_FILTER_WR_RX_CHAN_S 15 -#define FW_FILTER_WR_RX_CHAN_M 0x1 -#define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S) -#define FW_FILTER_WR_RX_CHAN_G(x) \ - (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M) -#define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U) - -#define FW_FILTER_WR_RX_RPL_IQ_S 0 -#define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff -#define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S) -#define FW_FILTER_WR_RX_RPL_IQ_G(x) \ - (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M) - -#define FW_FILTER_WR_MACI_S 23 -#define FW_FILTER_WR_MACI_M 0x1ff -#define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S) -#define FW_FILTER_WR_MACI_G(x) \ - (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M) - -#define FW_FILTER_WR_MACIM_S 14 -#define FW_FILTER_WR_MACIM_M 0x1ff -#define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S) -#define FW_FILTER_WR_MACIM_G(x) \ - (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M) - -#define FW_FILTER_WR_FCOE_S 13 -#define FW_FILTER_WR_FCOE_M 0x1 -#define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S) -#define FW_FILTER_WR_FCOE_G(x) \ - (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M) -#define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U) - -#define FW_FILTER_WR_FCOEM_S 12 -#define FW_FILTER_WR_FCOEM_M 0x1 -#define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S) -#define FW_FILTER_WR_FCOEM_G(x) \ - (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M) -#define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U) - -#define FW_FILTER_WR_PORT_S 9 -#define FW_FILTER_WR_PORT_M 0x7 -#define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S) -#define FW_FILTER_WR_PORT_G(x) \ - (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M) - -#define FW_FILTER_WR_PORTM_S 6 -#define FW_FILTER_WR_PORTM_M 0x7 -#define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S) -#define FW_FILTER_WR_PORTM_G(x) \ - (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M) - -#define FW_FILTER_WR_MATCHTYPE_S 3 -#define FW_FILTER_WR_MATCHTYPE_M 0x7 -#define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S) -#define FW_FILTER_WR_MATCHTYPE_G(x) \ - (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M) - -#define FW_FILTER_WR_MATCHTYPEM_S 0 -#define FW_FILTER_WR_MATCHTYPEM_M 0x7 -#define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S) -#define FW_FILTER_WR_MATCHTYPEM_G(x) \ - (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M) - -struct fw_ulptx_wr { - __be32 op_to_compl; - __be32 flowid_len16; - u64 cookie; -}; - -struct fw_tp_wr { - __be32 op_to_immdlen; - __be32 flowid_len16; - u64 cookie; -}; - -struct fw_eth_tx_pkt_wr { - __be32 op_immdlen; - __be32 equiq_to_len16; - __be64 r3; -}; - -struct fw_ofld_connection_wr { - __be32 op_compl; - __be32 len16_pkd; - __u64 cookie; - __be64 r2; - __be64 r3; - struct fw_ofld_connection_le { - __be32 version_cpl; - __be32 filter; - __be32 r1; - __be16 lport; - __be16 pport; - union fw_ofld_connection_leip { - struct fw_ofld_connection_le_ipv4 { - __be32 pip; - __be32 lip; - __be64 r0; - __be64 r1; - __be64 r2; - } ipv4; - struct fw_ofld_connection_le_ipv6 { - __be64 pip_hi; - __be64 pip_lo; - __be64 lip_hi; - __be64 lip_lo; - } ipv6; - } u; - } le; - struct fw_ofld_connection_tcb { - __be32 t_state_to_astid; - __be16 cplrxdataack_cplpassacceptrpl; - __be16 rcv_adv; - __be32 rcv_nxt; - __be32 tx_max; - __be64 opt0; - __be32 opt2; - __be32 r1; - __be64 r2; - __be64 r3; - } tcb; -}; - -#define FW_OFLD_CONNECTION_WR_VERSION_S 31 -#define FW_OFLD_CONNECTION_WR_VERSION_M 0x1 -#define FW_OFLD_CONNECTION_WR_VERSION_V(x) \ - ((x) << FW_OFLD_CONNECTION_WR_VERSION_S) -#define FW_OFLD_CONNECTION_WR_VERSION_G(x) \ - (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \ - FW_OFLD_CONNECTION_WR_VERSION_M) -#define FW_OFLD_CONNECTION_WR_VERSION_F \ - FW_OFLD_CONNECTION_WR_VERSION_V(1U) - -#define FW_OFLD_CONNECTION_WR_CPL_S 30 -#define FW_OFLD_CONNECTION_WR_CPL_M 0x1 -#define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S) -#define FW_OFLD_CONNECTION_WR_CPL_G(x) \ - (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M) -#define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U) - -#define FW_OFLD_CONNECTION_WR_T_STATE_S 28 -#define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf -#define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \ - ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S) -#define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \ - (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \ - FW_OFLD_CONNECTION_WR_T_STATE_M) - -#define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24 -#define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf -#define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \ - ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S) -#define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \ - (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \ - FW_OFLD_CONNECTION_WR_RCV_SCALE_M) - -#define FW_OFLD_CONNECTION_WR_ASTID_S 0 -#define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff -#define FW_OFLD_CONNECTION_WR_ASTID_V(x) \ - ((x) << FW_OFLD_CONNECTION_WR_ASTID_S) -#define FW_OFLD_CONNECTION_WR_ASTID_G(x) \ - (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M) - -#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15 -#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1 -#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \ - ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) -#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \ - (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \ - FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M) -#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \ - FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U) - -#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14 -#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1 -#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \ - ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) -#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \ - (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \ - FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M) -#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \ - FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U) - -enum fw_flowc_mnem { - FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ - FW_FLOWC_MNEM_CH, - FW_FLOWC_MNEM_PORT, - FW_FLOWC_MNEM_IQID, - FW_FLOWC_MNEM_SNDNXT, - FW_FLOWC_MNEM_RCVNXT, - FW_FLOWC_MNEM_SNDBUF, - FW_FLOWC_MNEM_MSS, - FW_FLOWC_MNEM_TXDATAPLEN_MAX, - FW_FLOWC_MNEM_TCPSTATE, - FW_FLOWC_MNEM_EOSTATE, - FW_FLOWC_MNEM_SCHEDCLASS, - FW_FLOWC_MNEM_DCBPRIO, - FW_FLOWC_MNEM_SND_SCALE, - FW_FLOWC_MNEM_RCV_SCALE, -}; - -struct fw_flowc_mnemval { - u8 mnemonic; - u8 r4[3]; - __be32 val; -}; - -struct fw_flowc_wr { - __be32 op_to_nparams; - __be32 flowid_len16; - struct fw_flowc_mnemval mnemval[0]; -}; - -#define FW_FLOWC_WR_NPARAMS_S 0 -#define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S) - -struct fw_ofld_tx_data_wr { - __be32 op_to_immdlen; - __be32 flowid_len16; - __be32 plen; - __be32 tunnel_to_proxy; -}; - -#define FW_OFLD_TX_DATA_WR_TUNNEL_S 19 -#define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S) - -#define FW_OFLD_TX_DATA_WR_SAVE_S 18 -#define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S) - -#define FW_OFLD_TX_DATA_WR_FLUSH_S 17 -#define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S) -#define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U) - -#define FW_OFLD_TX_DATA_WR_URGENT_S 16 -#define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S) - -#define FW_OFLD_TX_DATA_WR_MORE_S 15 -#define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S) - -#define FW_OFLD_TX_DATA_WR_SHOVE_S 14 -#define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S) -#define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U) - -#define FW_OFLD_TX_DATA_WR_ULPMODE_S 10 -#define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S) - -#define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6 -#define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \ - ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S) - -struct fw_cmd_wr { - __be32 op_dma; - __be32 len16_pkd; - __be64 cookie_daddr; -}; - -#define FW_CMD_WR_DMA_S 17 -#define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S) - -struct fw_eth_tx_pkt_vm_wr { - __be32 op_immdlen; - __be32 equiq_to_len16; - __be32 r3[2]; - u8 ethmacdst[6]; - u8 ethmacsrc[6]; - __be16 ethtype; - __be16 vlantci; -}; - -#define FW_CMD_MAX_TIMEOUT 10000 - -/* - * If a host driver does a HELLO and discovers that there's already a MASTER - * selected, we may have to wait for that MASTER to finish issuing RESET, - * configuration and INITIALIZE commands. Also, there's a possibility that - * our own HELLO may get lost if it happens right as the MASTER is issuign a - * RESET command, so we need to be willing to make a few retries of our HELLO. - */ -#define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) -#define FW_CMD_HELLO_RETRIES 3 - - -enum fw_cmd_opcodes { - FW_LDST_CMD = 0x01, - FW_RESET_CMD = 0x03, - FW_HELLO_CMD = 0x04, - FW_BYE_CMD = 0x05, - FW_INITIALIZE_CMD = 0x06, - FW_CAPS_CONFIG_CMD = 0x07, - FW_PARAMS_CMD = 0x08, - FW_PFVF_CMD = 0x09, - FW_IQ_CMD = 0x10, - FW_EQ_MNGT_CMD = 0x11, - FW_EQ_ETH_CMD = 0x12, - FW_EQ_CTRL_CMD = 0x13, - FW_EQ_OFLD_CMD = 0x21, - FW_VI_CMD = 0x14, - FW_VI_MAC_CMD = 0x15, - FW_VI_RXMODE_CMD = 0x16, - FW_VI_ENABLE_CMD = 0x17, - FW_ACL_MAC_CMD = 0x18, - FW_ACL_VLAN_CMD = 0x19, - FW_VI_STATS_CMD = 0x1a, - FW_PORT_CMD = 0x1b, - FW_PORT_STATS_CMD = 0x1c, - FW_PORT_LB_STATS_CMD = 0x1d, - FW_PORT_TRACE_CMD = 0x1e, - FW_PORT_TRACE_MMAP_CMD = 0x1f, - FW_RSS_IND_TBL_CMD = 0x20, - FW_RSS_GLB_CONFIG_CMD = 0x22, - FW_RSS_VI_CONFIG_CMD = 0x23, - FW_DEVLOG_CMD = 0x25, - FW_CLIP_CMD = 0x28, - FW_LASTC2E_CMD = 0x40, - FW_ERROR_CMD = 0x80, - FW_DEBUG_CMD = 0x81, -}; - -enum fw_cmd_cap { - FW_CMD_CAP_PF = 0x01, - FW_CMD_CAP_DMAQ = 0x02, - FW_CMD_CAP_PORT = 0x04, - FW_CMD_CAP_PORTPROMISC = 0x08, - FW_CMD_CAP_PORTSTATS = 0x10, - FW_CMD_CAP_VF = 0x80, -}; - -/* - * Generic command header flit0 - */ -struct fw_cmd_hdr { - __be32 hi; - __be32 lo; -}; - -#define FW_CMD_OP_S 24 -#define FW_CMD_OP_M 0xff -#define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S) -#define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M) - -#define FW_CMD_REQUEST_S 23 -#define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S) -#define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U) - -#define FW_CMD_READ_S 22 -#define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S) -#define FW_CMD_READ_F FW_CMD_READ_V(1U) - -#define FW_CMD_WRITE_S 21 -#define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S) -#define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U) - -#define FW_CMD_EXEC_S 20 -#define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S) -#define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U) - -#define FW_CMD_RAMASK_S 20 -#define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S) - -#define FW_CMD_RETVAL_S 8 -#define FW_CMD_RETVAL_M 0xff -#define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S) -#define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M) - -#define FW_CMD_LEN16_S 0 -#define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S) - -#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) - -enum fw_ldst_addrspc { - FW_LDST_ADDRSPC_FIRMWARE = 0x0001, - FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, - FW_LDST_ADDRSPC_SGE_INGC = 0x0009, - FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, - FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, - FW_LDST_ADDRSPC_TP_PIO = 0x0010, - FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, - FW_LDST_ADDRSPC_TP_MIB = 0x0012, - FW_LDST_ADDRSPC_MDIO = 0x0018, - FW_LDST_ADDRSPC_MPS = 0x0020, - FW_LDST_ADDRSPC_FUNC = 0x0028, - FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, -}; - -enum fw_ldst_mps_fid { - FW_LDST_MPS_ATRB, - FW_LDST_MPS_RPLC -}; - -enum fw_ldst_func_access_ctl { - FW_LDST_FUNC_ACC_CTL_VIID, - FW_LDST_FUNC_ACC_CTL_FID -}; - -enum fw_ldst_func_mod_index { - FW_LDST_FUNC_MPS -}; - -struct fw_ldst_cmd { - __be32 op_to_addrspace; - __be32 cycles_to_len16; - union fw_ldst { - struct fw_ldst_addrval { - __be32 addr; - __be32 val; - } addrval; - struct fw_ldst_idctxt { - __be32 physid; - __be32 msg_ctxtflush; - __be32 ctxt_data7; - __be32 ctxt_data6; - __be32 ctxt_data5; - __be32 ctxt_data4; - __be32 ctxt_data3; - __be32 ctxt_data2; - __be32 ctxt_data1; - __be32 ctxt_data0; - } idctxt; - struct fw_ldst_mdio { - __be16 paddr_mmd; - __be16 raddr; - __be16 vctl; - __be16 rval; - } mdio; - struct fw_ldst_cim_rq { - u8 req_first64[8]; - u8 req_second64[8]; - u8 resp_first64[8]; - u8 resp_second64[8]; - __be32 r3[2]; - } cim_rq; - union fw_ldst_mps { - struct fw_ldst_mps_rplc { - __be16 fid_idx; - __be16 rplcpf_pkd; - __be32 rplc255_224; - __be32 rplc223_192; - __be32 rplc191_160; - __be32 rplc159_128; - __be32 rplc127_96; - __be32 rplc95_64; - __be32 rplc63_32; - __be32 rplc31_0; - } rplc; - struct fw_ldst_mps_atrb { - __be16 fid_mpsid; - __be16 r2[3]; - __be32 r3[2]; - __be32 r4; - __be32 atrb; - __be16 vlan[16]; - } atrb; - } mps; - struct fw_ldst_func { - u8 access_ctl; - u8 mod_index; - __be16 ctl_id; - __be32 offset; - __be64 data0; - __be64 data1; - } func; - struct fw_ldst_pcie { - u8 ctrl_to_fn; - u8 bnum; - u8 r; - u8 ext_r; - u8 select_naccess; - u8 pcie_fn; - __be16 nset_pkd; - __be32 data[12]; - } pcie; - struct fw_ldst_i2c_deprecated { - u8 pid_pkd; - u8 base; - u8 boffset; - u8 data; - __be32 r9; - } i2c_deprecated; - struct fw_ldst_i2c { - u8 pid; - u8 did; - u8 boffset; - u8 blen; - __be32 r9; - __u8 data[48]; - } i2c; - struct fw_ldst_le { - __be32 index; - __be32 r9; - u8 val[33]; - u8 r11[7]; - } le; - } u; -}; - -#define FW_LDST_CMD_ADDRSPACE_S 0 -#define FW_LDST_CMD_ADDRSPACE_V(x) ((x) << FW_LDST_CMD_ADDRSPACE_S) - -#define FW_LDST_CMD_MSG_S 31 -#define FW_LDST_CMD_MSG_V(x) ((x) << FW_LDST_CMD_MSG_S) - -#define FW_LDST_CMD_CTXTFLUSH_S 30 -#define FW_LDST_CMD_CTXTFLUSH_V(x) ((x) << FW_LDST_CMD_CTXTFLUSH_S) -#define FW_LDST_CMD_CTXTFLUSH_F FW_LDST_CMD_CTXTFLUSH_V(1U) - -#define FW_LDST_CMD_PADDR_S 8 -#define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S) - -#define FW_LDST_CMD_MMD_S 0 -#define FW_LDST_CMD_MMD_V(x) ((x) << FW_LDST_CMD_MMD_S) - -#define FW_LDST_CMD_FID_S 15 -#define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S) - -#define FW_LDST_CMD_IDX_S 0 -#define FW_LDST_CMD_IDX_V(x) ((x) << FW_LDST_CMD_IDX_S) - -#define FW_LDST_CMD_RPLCPF_S 0 -#define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S) - -#define FW_LDST_CMD_LC_S 4 -#define FW_LDST_CMD_LC_V(x) ((x) << FW_LDST_CMD_LC_S) -#define FW_LDST_CMD_LC_F FW_LDST_CMD_LC_V(1U) - -#define FW_LDST_CMD_FN_S 0 -#define FW_LDST_CMD_FN_V(x) ((x) << FW_LDST_CMD_FN_S) - -#define FW_LDST_CMD_NACCESS_S 0 -#define FW_LDST_CMD_NACCESS_V(x) ((x) << FW_LDST_CMD_NACCESS_S) - -struct fw_reset_cmd { - __be32 op_to_write; - __be32 retval_len16; *** 3127 LINES SKIPPED ***