git: 331274591146 - stable/14 - ix/ixv: Match Tx writeback thresholds to iflib

The branch stable/14 has been updated by kbowling:

URL: https://cgit.FreeBSD.org/src/commit/?id=33127459114663c6a95a3e45c0416d54ea5c650e

commit 33127459114663c6a95a3e45c0416d54ea5c650e
Author:     Kevin Bowling <[email protected]>
AuthorDate: 2026-08-08 11:10:18 +0000
Commit:     Kevin Bowling <[email protected]>
CommitDate: 2026-08-22 00:57:51 +0000

    ix/ixv: Match Tx writeback thresholds to iflib
    
    PTHRESH controls when the device prefetches transmit descriptors,
    HTHRESH controls how many host descriptors must be ready, and WTHRESH
    controls completion writeback batching.
    
    iflib places RS on selected descriptors and reclaims through those
    checkpoints.  The data sheets require WTHRESH to be zero when software
    uses RS.  Clear WTHRESH while retaining the established PTHRESH 32 and
    HTHRESH 1 fetch policy.
    
    This also follows DPDK in pairing sparse RS descriptors with
    WTHRESH zero.  DPDK defaults to 32/0/0, while Linux ixgbevf uses
    32/1/8.  The 32/1/0 setting preserves FreeBSD's prefetch policy and the
    data-sheet requirement that HTHRESH be nonzero when PTHRESH is used.
    
    (cherry picked from commit 0baf0fabdb5e60e917458f85706707ee92683080)
---
 sys/dev/ixgbe/if_ix.c  | 10 ++++------
 sys/dev/ixgbe/if_ixv.c |  4 ++--
 sys/dev/ixgbe/ixgbe.h  |  8 ++++++++
 3 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/sys/dev/ixgbe/if_ix.c b/sys/dev/ixgbe/if_ix.c
index 4baaa040cbce..3aaee0905dad 100644
--- a/sys/dev/ixgbe/if_ix.c
+++ b/sys/dev/ixgbe/if_ix.c
@@ -4000,17 +4000,15 @@ ixgbe_if_init(if_ctx_t ctx)
 		struct tx_ring *txr = &tx_que->txr;
 
 		txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txr->me));
-		txdctl |= IXGBE_TXDCTL_ENABLE;
-		/* Set WTHRESH to 8, burst writeback */
-		txdctl |= (8 << 16);
+		txdctl &= ~IXGBE_TXDCTL_THRESH_MASK;
+		txdctl |= IXGBE_TXDCTL_ENABLE | IXGBE_TXDCTL_THRESH_DEFAULT;
 		/*
 		 * When the internal queue falls below PTHRESH (32),
 		 * start prefetching as long as there are at least
-		 * HTHRESH (1) buffers ready. The values are taken
-		 * from the Intel linux driver 3.8.21.
+		 * HTHRESH (1) buffers ready.  Leave WTHRESH at zero
+		 * so that writeback follows iflib's sparse RS bits.
 		 * Prefetching enables tx line rate even with 1 queue.
 		 */
-		txdctl |= (32 << 0) | (1 << 8);
 		IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txr->me), txdctl);
 	}
 
diff --git a/sys/dev/ixgbe/if_ixv.c b/sys/dev/ixgbe/if_ixv.c
index 556da3ffbb5a..14b63dbf1570 100644
--- a/sys/dev/ixgbe/if_ixv.c
+++ b/sys/dev/ixgbe/if_ixv.c
@@ -1349,9 +1349,9 @@ ixv_initialize_transmit_units(if_ctx_t ctx)
 		u32 txctrl, txdctl;
 		int j = txr->me;
 
-		/* Set WTHRESH to 8, burst writeback */
 		txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j));
-		txdctl |= (8 << 16);
+		txdctl &= ~IXGBE_TXDCTL_THRESH_MASK;
+		txdctl |= IXGBE_TXDCTL_THRESH_DEFAULT;
 		IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j), txdctl);
 
 		/* Set the HW Tx Head and Tail indices */
diff --git a/sys/dev/ixgbe/ixgbe.h b/sys/dev/ixgbe/ixgbe.h
index 90ce3e470686..2c53f417724f 100644
--- a/sys/dev/ixgbe/ixgbe.h
+++ b/sys/dev/ixgbe/ixgbe.h
@@ -121,6 +121,14 @@
 /* Alignment for rings */
 #define DBA_ALIGN		128
 
+/*
+ * iflib uses the RS bit to select the descriptors whose status it polls.
+ * Keep WTHRESH zero so the hardware honors RS, and retain the driver's
+ * established descriptor-prefetch settings.
+ */
+#define IXGBE_TXDCTL_THRESH_MASK		0x007f7f7f
+#define IXGBE_TXDCTL_THRESH_DEFAULT	((32 << 0) | (1 << 8))
+
 /*
  * This is the max watchdog interval, ie. the time that can
  * pass between any two TX clean operations, such only happening