Re: fwochi.c and bus_space_barrier()

Sean Bruno wrote:
> On Mon, 2009-04-20 at 21:38 +0200, Andreas Tobler wrote:
>> Sean Bruno wrote:
>>> On Mon, 2009-04-20 at 20:36 +0200, Andreas Tobler wrote:
>>>> resetting OHCI...done (loop=0)
>>>
>>> Can you recomplile with firewire_debug = 1 and resend the output?
>>>
>>> I'm interested in:
>>> device_printf(sc->fc.dev, "%s: OHCI_INT_REG_FAIL.\n", __func__);
>>>
>>> If that doesn't get printed, then I need to debug a bit further.
>> I always use firewire_debug=1, in the last try even > 1. All the traces 
>> I sent are with firewire_debug=1.
>>
>> I didn't see the above, I suspect the early OWRITE/READ in rddata are 
>> too early for the silicon. Unfortunately adding printf's there, cures 
>> the issue.
>>
>> Andreas
> 
> I *think* this section of fwphy_rddata() is suspect:
>         /*
>          * Setup command to PHY
>          */
>         fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
>         OWRITE(sc, OHCI_PHYACCESS, fun);
>         bus_space_barrier(sc->bst, sc->bsh, OHCI_PHYACCESS,
>                                 4, BUS_SPACE_BARRIER_WRITE);
> 
> 
> According to the specification, this access is illegal if SCLK has not
> started.  So, there's no way out of this error without a pause() after
> LPS is set in fwohci_probe_phy().  
> 
> Although this adventure did teach me a great deal regarding firewire.
> Thank you for the challenging problem.
> 
> Find the final version of my update attached.  Let me know what you find
> with it.

I'll have it working so far. Give some minutes to go over the code w/o 
debug.

Thanks,
Andreas

u60# kldload firewire
fwohci0: <Texas Instruments TSB12LV23> mem 
0x4008000-0x40087ff,0x400c000-0x400ff
ff irq 2008 at device 4.0 on pci0
fwohci0: latency timer 24 -> 32.
fwohci0: cache size 16 -> 16.
fwohci0: [ITHREAD]
fwohci0: OHCI version 1.0 (ROM=1)
fwohci0: No. of Isochronous channels is 4.
fwohci0: EUI64 00:10:74:60:00:00:ee:a9
fwohci0: resetting OHCI...done (loop=0)
fwohci0: fwphy_rddata:: 0x2, retry=6
fwohci0: fwphy_rddata:: 0x3, retry=6
fwohci0: Phy 1394a available S400, 3 ports.
fwohci0: fwphy_rddata:: 0x5, retry=6
fwohci0: Enable 1394a Enhancements
fwohci0: fwphy_rddata:: 0x5, retry=6
fwohci0: fwphy_rddata:: 0x2, retry=6
fwohci0: fwphy_rddata:: 0x4, retry=6
fwohci0: fwphy_rddata:: 0x4, retry=6
fwohci0: fwphy_rddata:: 0x4, retry=6
fwohci0: Link S400, max_rec 2048 bytes.
fwohci0: BUS_OPT 0xa002 -> 0xf800a002
fwohci0: fwohci_set_intr: 1
firewire0: <IEEE1394(FireWire) bus> on fwohci0
fwohci0: Initiate bus reset
fwohci0: fwphy_rddata:: 0x1, retry=6
fwohci0: fwphy_rddata:: 0x1, retry=6
fwohci0: fwohci_intr_core: BUS reset
fwohci0: fwohci_intr_core: node_id=0x00000000, SelfID Count=1, 
CYCLEMASTER mode
node:0 link:1 gap:5 spd:2 con:1 pwr:4 p0:1 p1:1 p2:1 i:1 m:0
firewire0: 1 nodes, maxhop <= 0 capable IRM irm(0)  (me)
fwohci0: fwohci_set_bus_manager: 0->0 (loop=0)
firewire0: bus manager 0
firewire0: fw_phy_config: root_node=-1 gap_count=5
fwohci0: fwohci_start: maxdesc 2
fwohci0: start AT DMA status=0
u60# firewire0: fw_bus_probe:iterate and invalidate all nodes
firewire0: fw_explore:found myself node(0) fc->nodeid(0) fc->max_node(0)
bus_explore done
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