Re: Chelsio / cxlv(4): strange messages, SR-IOV interface does not work

On 24/10/2024 00:43, Navdeep Parhar wrote:
> On Tue, Oct 22, 2024 at 11:21 PM Lexi Winter <[email protected] 
> <mailto:[email protected]>> wrote:

>     however, trying to assign an IP address causes immediate problems:
> 
>     root@lily:~ # ifconfig cxlv0 inet6 2001:8b0:aab5:7::10/64
>     root@lily:~ # Oct 23 06:16:07 lily kernel: cxlv0: a looped back NS
>     message is detected during DAD for fe80:3::444:3fff:fee7:6030.  Another
>     DAD probes are being sent.

> You can disable IPv6 DAD as a workaround for this issue.  The problem is 
> that the VF's multicast tx is getting reflected back to it by the 
> internal switch when it shouldn't.
> 
> # sysctl net.inet6.ip6.dad_count=0

thanks Navdeep, after enabling this, networking is working in the VM.

however, i can't tell if VLAN filtering is supposed to be working for VF 
interfaces.  from looking at src, it seems like after a couple of recent 
commits (c57c261790 and 1389314d5) this should be supported.  so i 
configured a VLAN restriction in the iovctl.conf:

PF {
         device : "cxl3";
         num_vfs : 16;
}

DEFAULT {
         passthrough : true;
         vlan : 111;
}

VF-0 {
         passthrough : true;
         vlan : 111;
         mac-addr : "06:00:00:00:05:a0"
}

configuring cxlv0.111 in the VM works and the VM can communicate on VLAN 
111, but if i look at tcpdump inside the VM, i also see untagged traffic 
on the host port:

21:16:23.874161 74:4d:28:08:81:f6 > 01:80:c2:00:00:0e, ethertype LLDP 
(0x88cc), length 177: LLDP, length 163: c1.i.lfns.org.uk

as well as traffic for VLAN 3003, which is the bhyve host's VLAN:

21:14:28.550117 06:00:00:00:06:01 > 01:00:5e:00:00:0d, ethertype 802.1Q 
(0x8100), length 72: vlan 3003, p 0, ethertype IPv4 (0x0800), 
172.22.0.37 > 224.0.0.13: PIMv2, Hello, length 34

so, it seems like there's no actual VLAN filtering happening in the 
hardware.  is there a sysctl that needs to be enabled to work this?  (i 
did have a quick look through the hw.cxgbe MIB but didn't see anything 
obvious.)

or is this only supported for T4 ASICs, not T5?