cpudep_ap_early_bootstrap: IBM970 SPR_HID4 and SPR_HID5 updates are not following documented, 970-family-specific rules

cpudep_ap_early_bootstrap has:

        switch (mfpvr() >> 16) {
        case IBM970:
        case IBM970FX:
        case IBM970MP:
                /* Restore HID4 and HID5, which are necessary for the MMU */
                        
#ifdef __powerpc64__
                mtspr(SPR_HID4, bsp_state[2]); powerpc_sync(); isync();
                mtspr(SPR_HID5, bsp_state[3]); powerpc_sync(); isync();
#else
. . .



But 970MP_um.2008MAR07_pub.pdf reports some explicit instruction
sequences and words about more instruction if some specific bits
might change:

QUOTE
	• The following sequence must be used when modifying HID4:

sync
mtspr HID4,Rx
isync

When HID4[23] is changed, the previous sequence should be preceded by a Move to Segment Register (mtsr) and Synchronize (sync) instruction, which will cause the effective-to-real-address translations (ERATs) to be flushed.

	• The following sequence must be used when modifying HID5:

sync
mtspr HID5,Rx
isync

Whenever HID5[56] or HID5[57] is changed, the entire instruction cache must be flushed to ensure that any succeeding Data Cache Block Set to Zero (dcbz) instruction is executed in the context of the new HID5 bit settings.
END QUOTE

===
Mark Millard
marklmi at yahoo.com
( dsl-only.net went
away in early 2018-Mar)

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