Re: PCI range checking under qemu-system-sparc64
Marius Strobl <[email protected]>
| Newsgroups | gmane.os.freebsd.devel.sparc |
|---|---|
| Message-ID | <[email protected]> |
On Wed, Sep 23, 2015 at 09:19:53AM +0100, Mark Cave-Ayland wrote: > > I've had a quick look through the relevant PDFs and the definitions I > have for tick/stick are this: > > tick: > bit 63: NPT (Non-Privileged Trap enable - defaults to 1) > bits 62 - 0: CPU cycle counter > > tick_cmpr: > bit 63: Interrupt disable (1 = no interrupt) > bits 62 - 0: counter compare value > > stick: > bit 63: Reserved (reads 0, no write) > bits 62 - 0: stick register count value I cannot confirm that, the specification for the first sun4u CPU having a %stick register (UltraSPARC III, see 1, p. 6-105) up to the latest architecture specification (see 2, p. 60) say that bit 32 of %stick is NPT, just as with %tick. Same for the specification the Fujitsu SPARC64 processors follow (3, p. 90). Marius 1: http://www.ece.cmu.edu/~protoflex/lib/exe/fetch.php?media=documentation:usiiiv2.pdf 2: http://www.oracle.com/technetwork/systems/hardware/usparcarchdoc2007-329425.pdf 3: https://www.fujitsu.com/global/Images/JPS1-R1.0.4-Common-pub.pdf _______________________________________________ [email protected] mailing list https://lists.freebsd.org/mailman/listinfo/freebsd-sparc64 To unsubscribe, send any mail to "[email protected]"