Re: kern/59876 (igc0: unable to initialize)

The following reply was made to PR kern/59876; it has been noted by GNATS.

From: Shinichi Doyashiki <[email protected]>
To: [email protected]
Cc: 
Subject: Re: kern/59876 (igc0: unable to initialize)
Date: Wed, 22 Jul 2026 06:25:03 +0900

 recent -current shows autoconfiguration error for kernel without PCI ADDR FIXUP
 option.  the kernel with PCI ADDR FIXUP option shows normal attach messages.
 the hardware used is the ASROCK J4125M and the i226-V add-on card.
 
 without PCI ADDR FIXUP option
 ...
 [     1.038633] pci1 at ppb0 bus 1
 [     1.038633] pci1: i/o space, memory space enabled, rd/line, wr/inv ok
 [     1.038633] igc0 at pci1 dev 0 function 0, 64-bit DMA: Intel(R) Ethernet 
 Controller I226-V (rev. 0x04)
 [     1.038633] igc0: autoconfiguration error: unable to initialize
 ...
 
 with PCI ADDR FIXUP option
 ...
 [   1.0385304] pci1 at ppb0 bus 1 
 [   1.0385304] igc0 at pci1 dev 0 function 0: Intel(R) Ethernet Controller 
 I226-V (rev. 0x04)
 [   1.0385304] igc0: txrx interrupting at msix2 vec 0
 [   1.0385304] igc0: txrx interrupting at msix2 vec 1
 [   1.0385304] igc0: txrx interrupting at msix2 vec 2
 [   1.0385304] igc0: txrx interrupting at msix2 vec 3
 [   1.0385304] igc0: link interrupting at msix2 vec 4
 [   1.0385304] igc0: PHY: OUI 0x984fee model 0x0005, rev. 8, PHY FW version 
 0x8877
 [   1.0385304] igc0: NVM image version 2.14, EtrackID 8000028d
 ...
 
 Expansion ROM BAR is not moved from 0xa1100000
 by PCI ADDR FIXUP; disabled by BIOS and kept it
 disabled by kernel in both cases;
 BAR 0x10 was moved from 0xa1100000 to 0xa1200000;
 BAR 0x1C was moved from 0xa1200000 to 0xa1300000;
 by PCI ADDR FIXUP kernel option.
 Is it not permitted for the region indicated by a PCI Expansion
 ROM BAR in the disabled state to overlap with a standard MMIO BAR?
 
 # pcictl pci1 dump -d 0 > after-fixup
 # diff -u before-fixup after-fixup 
 --- before-fixup        2026-07-21 13:34:02.176913247 +0000
 +++ after-fixup 2026-07-21 13:43:52.013368953 +0000
 @@ -40,20 +40,20 @@
      Cache Line Size: 64bytes (0x10)
  
    Type 0 ("normal" device) header:
 -    0x10: 0xa1100000 0x00000000 0x00000000 0xa1200000
 +    0x10: 0xa1200000 0x00000000 0x00000000 0xa1300000
      0x20: 0x00000000 0x00000000 0x00000000 0x00008086
      0x30: 0xa1100000 0x00000040 0x00000000 0x000001ff
  
      Base address register at 0x10
        type: 32-bit nonprefetchable memory
 -      base: 0xa1100000
 +      base: 0xa1200000
      Base address register at 0x14
        not implemented
      Base address register at 0x18
        not implemented
      Base address register at 0x1c
        type: 32-bit nonprefetchable memory
 -      base: 0xa1200000
 +      base: 0xa1300000
      Base address register at 0x20
        not implemented
      Base address register at 0x24
 @@ -250,7 +250,7 @@
      Message Control register: 0x0004
        Table Size: 5
        Function Mask: off
 -      MSI-X Enable: off
 +      MSI-X Enable: on
      Table offset register: 0x00000003
        Table offset: 0x00000000
        BIR: 0x3
 @@ -262,7 +262,7 @@
      0x40: 0xc8235001 0x00002008 0x00000000 0x00000000
      0x50: 0x01807005 0x00000000 0x00000000 0x00000000
      0x60: 0x00000000 0x00000000 0x00000000 0x00000000
 -    0x70: 0x0004a011 0x00000003 0x00002003 0x00000000
 +    0x70: 0x8004a011 0x00000003 0x00002003 0x00000000
      0x80: 0x00000000 0x00000000 0x00000000 0x00000000
      0x90: 0x00000000 0x00000000 0x00000000 0xffffffff
      0xa0: 0x00020010 0x10008cc2 0x00102830 0x00415812