PR/60619 CVS commit: src/sys/arch/x86/x86

The following reply was made to PR port-amd64/60619; it has been noted by GNATS.

From: "Andrius Varanavicius" <[email protected]>
To: [email protected]
Cc: 
Subject: PR/60619 CVS commit: src/sys/arch/x86/x86
Date: Tue, 25 Aug 2026 21:06:50 +0000

 Module Name:	src
 Committed By:	andvar
 Date:		Tue Aug 25 21:06:50 UTC 2026
 
 Modified Files:
 	src/sys/arch/x86/x86: identcpu.c
 
 Log Message:
 Decode L2 cache associativity for VIA CPUs using the AMD cache lookup table for
 the 0x80000006 CPUID function associativity value.
 
 Use `cpuid leaf 4' to get cache parameters for Zhaoxin and late VIA CPU models.
 
 VIA datasheets mention that associativity is stored as a decimal value. However,
 in practice, it is encoded the AMD way and does not store the actual value.
 Using the raw value leads to an incorrect CPU colors calculation, causing a
 panic on KX-7000 (since the result is not a power of two) and incorrect CPU
 colors values on other CPU models (e.g. as visible in `vmstat -s').
 Decoding value using the AMD cache lookup table produces correct values in all
 cases I have tested or verified using CPUID dumps available online.
 
 Additionally, Zhaoxin and late VIA CPUs (CNQ and newer) prefer the Intel
 `cpuid leaf 4' function to get cache parameters. Check whether cpuid_level
 is equal to or greater than 4 to identify these CPUs and override cache values
 (including L1) by calling cpu_dcp_cacheinfo(ci, 4). L3 cache information is
 available only through this method.
 
 Fixes PR kern/60619
 
 Similar changes will be committed separately to the cpuctl utility.
 
 pullups to netbsd-11 and netbsd-10 are needed.
 
 Thanks to skrll@ for comments on the patch.
 
 
 To generate a diff of this commit:
 cvs rdiff -u -r1.141 -r1.142 src/sys/arch/x86/x86/identcpu.c
 
 Please note that diffs are not public domain; they are subject to the
 copyright notices on the relevant files.