Re: hppa lazy FPU switching and QEMU bugs

On 05/08/2026 09:34, Martin Husemann wrote:
> Can someone describe the CPU flags used on hppa to enable the FPU and
> to cause that "assisted emulation" exception - are they different?
>
> Is the "assisted emulation" just an optimization and we could fall back
> to completely disabling FPU if running under qemu?

http://ftp.parisc-linux.org/docs/arch/parisc2.0.pdf

Coprocessor Configuration Register
The CCR (Coprocessor Configuration Register) is an 8-bit control register (within CR 10 bits 24..31)
that is used to indicate the presence and usability of a hardware implementation of a coprocessor. Bits 0
and 1 in the CCR correspond to the floating-point coprocessor and bit 2 in the CCR corresponds to the
performance monitor coprocessor. For all other bits in the CCR, CCR{i} corresponds to an undefined
coprocessor with a unit identifier that is the same as the bit position, that is the coprocessor with uid i.
Execution of any floating-point instruction with CCR{0} and CCR{1} not set to the same value is an
undefined operation. Execution of a coprocessor operation instruction (major opcode 0x0C) with
CCR{0}, CCR{1}, and the uid field in the instruction all set to 1 is an undefined operation.
When CCR{i} is 1, the coprocessor with uid i is implied to be present and usable.

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