Re: Intel 82801H SATA interrupt issues

Emmanuel Dreyfus <[email protected]>
Newsgroups gmane.os.netbsd.devel.kernel
Message-ID <[email protected]> 
On Sat, Aug 31, 2024 at 08:07:36AM -0500, Jonathan A. Kollasch wrote:
> Could you get us the pcictl dump output of both piixide(4) PCI functions?
> Something like `pcictl pci0 dump -d 31 -f 2` and `pcictl pci0 dump -d 31 -f 5`.

Here it is:
PCI configuration registers:
  Common header:
    0x00: 0x28208086 0x02b00007 0x01018f02 0x00000000

    Vendor Name: Intel (0x8086)
    Device Name: 82801H SATA Controller (0x2820)
    Command register: 0x0007
      I/O space accesses: on
      Memory space accesses: on
      Bus mastering: on
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): off
      Fast back-to-back transactions: off
      Interrupt disable: off
    Status register: 0x02b0
      Immediate Readiness: off
      Interrupt status: inactive
      Capability List support: on
      66 MHz capable: on
      User Definable Features (UDF) support: off
      Fast back-to-back capable: on
      Data parity error detected: off
      DEVSEL timing: medium (0x1)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: off
    Class Name: mass storage (0x01)
    Subclass Name: IDE (0x01)
    Interface: 0x8f
    Revision ID: 0x02
    BIST: 0x00
    Header Type: 0x00 (0x00)
    Latency Timer: 0x00
    Cache Line Size: 0bytes (0x00)

  Type 0 ("normal" device) header:
    0x10: 0x0000fa01 0x0000f901 0x0000f801 0x0000f701
    0x20: 0x0000f601 0x0000f501 0x00000000 0x28208086
    0x30: 0x00000000 0x00000070 0x00000000 0x0000020f

    Base address register at 0x10
      type: I/O
      base: 0x0000fa00
    Base address register at 0x14
      type: I/O
      base: 0x0000f900
    Base address register at 0x18
      type: I/O
      base: 0x0000f800
    Base address register at 0x1c
      type: I/O
      base: 0x0000f700
    Base address register at 0x20
      type: I/O
      base: 0x0000f600
    Base address register at 0x24
      type: I/O
      base: 0x0000f500
    Cardbus CIS Pointer: 0x00000000
    Subsystem vendor ID: 0x8086
    Subsystem ID: 0x2820
    Expansion ROM Base Address Register: 0x00000000
      base: 0x00000000
      Expansion ROM Enable: off
      Validation Status: Validation not supported
      Validation Details: 0x0
    Capability list pointer: 0x70
    Reserved @ 0x38: 0x00000000
    Maximum Latency: 0x00
    Minimum Grant: 0x00
    Interrupt pin: 0x02 (pin B)
    Interrupt line: 0x0f

  Capability register at 0x70
    type: 0x01 (Power Management)

  PCI Power Management Capabilities Register
    Capabilities register: 0x4003
      Version: 1.2
      PME# clock: off
      Device specific initialization: off
      3.3V auxiliary current: self-powered
      D1 power management state support: off
      D2 power management state support: off
      PME# support D0: off
      PME# support D1: off
      PME# support D2: off
      PME# support D3 hot: on
      PME# support D3 cold: off
    Control/status register: 0x00000008
      Power state: D0
      PCI Express reserved: off
      No soft reset: on
      PME# assertion: disabled
      Data Select: 0
      Data Scale: 0
      PME# status: off
    Bridge Support Extensions register: 0x00
      B2/B3 support: off
      Bus Power/Clock Control Enable: off
    Data register: 0x00

  Device-dependent header:
    0x40: 0x8000a307 0x00000000 0x00010001 0x00000000
    0x50: 0x00000000 0x00001000 0x00000000 0x00000000
    0x60: 0x00000000 0x00000000 0x00000000 0x00000000
    0x70: 0x40030001 0x00000008 0x00000000 0x00000000
    0x80: 0x00007005 0x00000000 0x00000000 0x00000000
    0x90: 0x81030000 0x40000180 0x00000000 0x00000001
    0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xc0: 0x00000000 0x00000005 0x00000000 0x00000000
    0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xf0: 0x00000000 0x00000000 0x00030f86 0x00000000

PCI configuration registers:
  Common header:
    0x00: 0x28258086 0x02b00005 0x01018502 0x00000000

    Vendor Name: Intel (0x8086)
    Device Name: 82801H SATA Controller (0x2825)
    Command register: 0x0005
      I/O space accesses: on
      Memory space accesses: off
      Bus mastering: on
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): off
      Fast back-to-back transactions: off
      Interrupt disable: off
    Status register: 0x02b0
      Immediate Readiness: off
      Interrupt status: inactive
      Capability List support: on
      66 MHz capable: on
      User Definable Features (UDF) support: off
      Fast back-to-back capable: on
      Data parity error detected: off
      DEVSEL timing: medium (0x1)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: off
    Class Name: mass storage (0x01)
    Subclass Name: IDE (0x01)
    Interface: 0x85
    Revision ID: 0x02
    BIST: 0x00
    Header Type: 0x00 (0x00)
    Latency Timer: 0x00
    Cache Line Size: 0bytes (0x00)

  Type 0 ("normal" device) header:
    0x10: 0x0000f301 0x0000f201 0x0000f101 0x0000f001
    0x20: 0x0000ef01 0x0000ee01 0x00000000 0x28258086
    0x30: 0x00000000 0x00000070 0x00000000 0x0000020f

    Base address register at 0x10
      type: I/O
      base: 0x0000f300
    Base address register at 0x14
      type: I/O
      base: 0x0000f200
    Base address register at 0x18
      type: I/O
      base: 0x0000f100
    Base address register at 0x1c
      type: I/O
      base: 0x0000f000
    Base address register at 0x20
      type: I/O
      base: 0x0000ef00
    Base address register at 0x24
      type: I/O
      base: 0x0000ee00
    Cardbus CIS Pointer: 0x00000000
    Subsystem vendor ID: 0x8086
    Subsystem ID: 0x2825
    Expansion ROM Base Address Register: 0x00000000
      base: 0x00000000
      Expansion ROM Enable: off
      Validation Status: Validation not supported
      Validation Details: 0x0
    Capability list pointer: 0x70
    Reserved @ 0x38: 0x00000000
    Maximum Latency: 0x00
    Minimum Grant: 0x00
    Interrupt pin: 0x02 (pin B)
    Interrupt line: 0x0f

  Capability register at 0x70
    type: 0x01 (Power Management)

  PCI Power Management Capabilities Register
    Capabilities register: 0x4003
      Version: 1.2
      PME# clock: off
      Device specific initialization: off
      3.3V auxiliary current: self-powered
      D1 power management state support: off
      D2 power management state support: off
      PME# support D0: off
      PME# support D1: off
      PME# support D2: off
      PME# support D3 hot: on
      PME# support D3 cold: off
    Control/status register: 0x00000008
      Power state: D0
      PCI Express reserved: off
      No soft reset: on
      PME# assertion: disabled
      Data Select: 0
      Data Scale: 0
      PME# status: off
    Bridge Support Extensions register: 0x00
      B2/B3 support: off
      Bus Power/Clock Control Enable: off
    Data register: 0x00

  Device-dependent header:
    0x40: 0x8000a307 0x00000000 0x00010001 0x00000000
    0x50: 0x00000000 0x00001000 0x00000000 0x00000000
    0x60: 0x00000000 0x00000000 0x00000000 0x00000000
    0x70: 0x40030001 0x00000008 0x00000000 0x00000000
    0x80: 0x00000000 0x00000000 0x00000000 0x00000000
    0x90: 0x01030000 0x00000000 0x00000000 0x00000000
    0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xf0: 0x00000000 0x00000000 0x00030f86 0x00000000


-- 
Emmanuel Dreyfus
[email protected]
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