Re: Boot order
"Toru Nishimura" <[email protected]> Mon, 20 Feb 2006 13:09:36 +0900
| Newsgroups | gmane.os.netbsd.devel.ports |
|---|---|
| Organization | ALKYL Technology |
| Message-ID | <000401c635d3$77f58af0$1318a8c0@paq11> |
> I agree. The problem being here occurs when the data-flow and > relationship between devices doesn't match the idea of a single, > rooted device hierarchy. And the node traversing order is hardly under control even if _deferred twist is introduced. For NV store argument, it's just a sort of how to fetch "operating environment," and no more. Having i2c bus node will end up with tree distortion. Any of a-few-wire controlled chips (enumerate as much as possible) is pure electronical invention which leaves tremendous burden for software developers. PLS access how much CPU cycle, brach-loop, miss-prediction, cache-miss and long critical section to wait for s-l-o-w devices AND the entire precious software developers time wasted to handle them correctly. They're awful invention and cannot be smart to do it right. Unless interrupt generating device (like keypad) is hooked, it'd be hardly justified to have "intermediate bus" node to encapsulate. Toru Nishimura/ALKYL Technology