Re: MP interrupt problems with PRIMERGY RX300 --- Success
Peter O'Kane <[email protected]> Mon, 20 Dec 2004 18:30:45 +0000
| Newsgroups | gmane.os.netbsd.ports.i386,gmane.os.netbsd.devel.smp |
|---|---|
| Message-ID | <[email protected]> |
This was a deduction from the observed behavior, i.e. everything worked in the single physical processor case (with/without HTT enabled) and was independent of which single physical processor was enabled. therefore it must be something to do with the not fully fired up second physical processor. Abstract question: Does it make sense to specify "processor executing at lowest priority" along with a physical address specifying only one processor? Answer: Probably not. Experiment: Change the definitions to make certain fixed rather than low priority is used. Result: It boots on the RX300. I have done a kernel build with all 4 processors running with no problems. Tucked away on page 8-27 Vol 3 of the IA-32 Intel(R) Architecture Software Developer's Manual is the following little gem: "A broadcast IPI (bits 28-31 of the MDA are 1's) or I/O subsystem initiated interrupt with lowest priority delivery mode is not supported in physical destination mode and must not be configured by software. Also, for any non-broadcast IPI or I/O subsystem initiated interrupt with lowest priority delivery mode, software must ensure that APICs defined in the interrupt address are present and enabled to receive interrupts." --On 20 December 2004 10:29 +0100 Frank van der Linden <[email protected]> wrote: > On Fri, Dec 17, 2004 at 05:01:30PM +0000, Peter O'Kane wrote: >> O.K. I have got my RX300 running with all four logical processors. >> Problem appears to be that, at the point where the ioapics are enabled, >> the local apic on the second physical processor is not properly >> initialized to take part in the negotiations needed for lowest priority >> delivery mode and that, even though only the BSP is specified as the >> interrupt target the LOPRI delivery mode is being specified. > > That's an interesting observation.. I wasn't actually aware that this > could happen. Where in the Intel documentation is this described? It > may explain some other problems, and I'd like to fix it. > > - Frank Peter O'Kane E-mail:[email protected] Information Technology Department, Voice: +353 91 492527 National University of Ireland, Galway. Fax: +353 91 494501