Re: Re: Re: BCM5301x SMP

Hi

> ----- Original Message -----
> 
> From: "Christoph Badura" <[email protected]>
> To: "や もり" <[email protected]>
> Cc: "[email protected]" <[email protected]>
> Date: 2025/07/02 水 03:49
> Subject: Re: Re: BCM5301x SMP
> 
> 
> Sorry for not answering earlier.
> 
> I'll reorder the text in your message a little so that I can reply to the
> more important bits first.
> 
> On Sat, Jun 28, 2025 at 04:49:05PM +0900, Mori Hiroki wrote:
> 
> > problem case.
> > 
> > [   4.5676083] WARNING: CHECK AND RESET THE DATE!
> > init: fatal sign[  34.7399758] panic: kpsignal2(20)
> > [  34.7399758] cpu0: Begin traceback...
> > ...
> > db{0}> ps 
> > PID     LID S CPU     FLAGS       STRUCT LWP *               NAME WAIT
> > 1         1 3   1       180           9fde9d00               init wait
> 
> Signal 20 is SIGCHLD.  Receiving this signal is normal.  And init(8)
> ignores it.  It certainly doesn't print "fatal signal" for it.  Are you
> sure this is the problem case?

Yes

This is console move.

https://youtu.be/nNyvgaazL5Q?si=cuZEU78dWmA0OLko

Thanks

Hiroki Mori

> 
> > no problem case.
> > 
> > [   4.5775946] WARNING: CHECK AND RESET THE DATE!
> > [   4.5999814] 1.1(init): trap: signo=10 code=2 addr=0x7fffeb58 trap=0x1c06
> > [   4.5999814] r0=7fffeff0 r1=00000000 r2=00000000 r3=00000000
> > [   4.6136304] r4=00000000 r5=00000000 r6=00000000 r7=00000000
> > [   4.6136304] r8=00000000 r9=00000000 rA=00000000 rB=00000000
> > [   4.6250933] ip=7fffeb58 sp=7fffeb58 lr=7bed0588 pc=7bed0588 spsr=00000010
> > [   4.6320815] panic: kpsignal2(10)
> > [   4.6320815] cpu0: Begin traceback...
> > ...
> > db{0}> ps
> > PID     LID S CPU     FLAGS       STRUCT LWP *               NAME WAIT
> > 1    >    1 7   0         0           9fde64c0               init
> 
> Signal 10 is SIGBUS.  That would be the real problem, IMHO.  googling for
> 'arm traps "0x1c06"' I found this:
> https://linux-arm-kernel.infradead.narkive.com/OdBwOmnQ/patch-v4-0-4-arm-bcm5301x-initial-support-for-the-bcm5301x-bcm470x-socs-with-arm-cpu#post4
> https://linux-arm-kernel.infradead.narkive.com/MWaNp4Pi/patch-v6-0-4-arm-bcm5301x-initial-support-for-the-bcm5301x-bcm470x-socs-with-arm-cpu#post4
> 
> Seems like "-current" Linux still contains an updated version of this
> workaround:
> 
> https://github.com/torvalds/linux/blob/66701750d5565c574af42bef0b789ce0203e3071/arch/arm/mach-bcm/bcm_5301x.c#L22
> 
> > I add this code.
> 
> > BCM5301x is non FDT. Where I add cache opration?
> 
> I have no idea where you would need to add the cache operation in this
> particular case.  I was hoping that maybe that particular change from 5
> years ago might help you to identify the general area in your code.  If it
> turns out to be a cache invalidation issue.  But I guess the point is moot.
> 
> --chris
>