structuring interrupt machine in ppoea-renovation

Attention for cat owners,

There is much interesting activities is going in "ppoea-renovation"
branch and your cats could be benefited by feeding the idea from
it.

The HW has slots for PCI and ISA which are to mimic standard
PC-alike configuration with ALi1543C and 21285 footbridge.
Constructing the whole interrupt machinery has been a hard
practice since mixing different breed interrupt HW designs into a single
working one would bring forehead-bang'ng-at-neary-by-wall burdens.
To solve the issue Macheal Lorenz and Tim Rightnour made a single,
unified and extensible construct for PPC to house multiple interrupt HW
sources;

- can cope well with interrupt source > 32.
- can add and cascade many interrupt HW sources.
- can do the smart things for spl(9) and softintr(9), e.g., multiple NICs
  populated separately in PCI/ISA slots (and possiblely ones build
  inside SoC core) can be handled in the right fashion by IPL_NET.

PLS take a glance at powerpc/pic/ directory and how prep/macppc
and other less-complicated ppc ports ultilize the construct, and learn
the way how it can be modelled for cats.

I'm planning to build 2nd-stage netboot loader to make cats possible
to do DHCP/NFS netboot.  The goal is to provide true ELF kernel
loading with DDB symbol table and no size limit.

Toru Nishimura / ALKYL Technology / [email protected]