Re: Super-H machine language issues

der Mouse <[email protected]> wrote:

> There are a number of floating-point instructions which appear to me to
> be ambiguous.  For example, page 271 says (slightly reformatted)
> 
>        FMOV.S  FRm,@(R0,Rn)            1111nnnnmmmm0111
> 
> but page 275 says (ditto)
> 
>        FMOV    XDm,@(R0,Rn)            1111nnnnmmm10111
> 
> The first is valid only when SZ is 0 and the latter when PR is 1, but I
> see no reason those can't both be true at the same time - and the
> functionality of those two instructions is not the same.  (They store
> to the same address, but they store different amounts of data and they
> get the data to be stored from different registers.)  I can't believe
> the hardware reads the programmer's mind to divine the intent of the
> code, leaving me wondering.

Where does the manual say that the latter is valid only when PR is 1?
I checked sh4 ISA manual and update manuals from Renesas and I can't
see anything like that.

If you look at all the cases:

  FMOV.S  FRm,@(R0,Rn)            1111nnnnmmmm0111
  FMOV    DRm,@(R0,Rn)            1111nnnnmmm00111
  FMOV    XDm,@(R0,Rn)            1111nnnnmmm10111

you can clearly see the pattern.  There's really only one instruction
1111nnnnmmmm0111 that in 32-bit transfer mode (SZ=1) operates on FRm.
In 64-bit transfer mode the register number must be even, since DRm is
just a name for the { FRm, FRm+1 } pair.  So when 1111nnnnmmmm0111 is
executed with SZ=1 and the least significant bit of "mmmm" that
encodes the register number is 0, it operates on DRm, i.e. on the
current bank, but when it's 1 - it operates on XD[m&~1]m i.e. on the
other bank.

-uwe