aupcmcia on OMSAL400 work
KIYOHARA Takashi <[email protected]>
| Newsgroups | gmane.os.netbsd.ports.evbmips |
|---|---|
| Message-ID | <[email protected]> |
Hi! all, aupcmcia on OMSAL400 work. I'm tested wd via wdc at pcmcia. My OMSAL400 is booted root on wd0a. fdisk(8) and disklabel(8) is OK! aupcmcia0 at aubus0 addr 0x0: Alchemy PCMCIA, 1 slots pcmcia0 at aupcmcia0 socket 0 irq 35, CF connector Type2 on Static BUS#3 ... snip ... wdc0 at pcmcia0 function 0: <TRANSCEND, TS512MCF80> wdc0: i/o mapped mode slot 0 interrupting on irq 35 ../../../../dev/pcmcia/wdc_pcmcia.c: 322: May we sleep? <-- see kern/33137 config_pending_incr(9) is necessary for us perhaps. or use delay(9)? atabus0 at wdc0 channel 0 wd0 at atabus0 drive 0: <TRANSCEND> wd0: drive supports 1-sector PIO transfers, LBA addressing wd0: 488 MB, 993 cyl, 16 head, 63 sec, 512 bytes/sect x 1000944 sectors wd0: drive supports PIO mode 4 root device: wd0 dump device (default wd0b): file system (default generic): root on wd0a dumps on wd0b slot 0 interrupting on irq 35 slot 0 interrupting on irq 35 mountroot: trying ffs... root file system type: ffs I will commit it next week end if it is unquestionable. Thanks, -- kiyohara
omsal400_pcmcia.diff
(text/plain, 3.1 KB)
? compile/OMSAL400
Index: alchemy/omsal400.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/alchemy/omsal400.c,v
retrieving revision 1.3
diff -u -r1.3 omsal400.c
--- alchemy/omsal400.c 1 Mar 2006 20:21:41 -0000 1.3
+++ alchemy/omsal400.c 24 Mar 2006 17:45:43 -0000
@@ -41,6 +41,8 @@
#include <sys/param.h>
#include <machine/bus.h>
#include <machine/locore.h>
+#include <mips/alchemy/dev/augpiovar.h>
+#include <mips/alchemy/dev/aupcmciavar.h>
#include <evbmips/alchemy/obiovar.h>
#include <evbmips/alchemy/board.h>
#include <evbmips/alchemy/omsal400reg.h>
@@ -55,11 +57,27 @@
pci_intr_handle_t *);
static void omsal400_poweroff(void);
static void omsal400_reboot(void);
+static bus_addr_t omsal400_slot_offset(int);
+static int omsal400_slot_irq(int, int);
+static void omsal400_slot_enable(int);
+static void omsal400_slot_disable(int);
+static int omsal400_slot_status(int);
+static const char *omsal400_slot_name(int);
static const struct obiodev omsal400_devices[] = {
{ NULL },
};
+static struct aupcmcia_machdep omsal400_pcmcia = {
+ 1, /* nslots */
+ omsal400_slot_offset,
+ omsal400_slot_irq,
+ omsal400_slot_enable,
+ omsal400_slot_disable,
+ omsal400_slot_status,
+ omsal400_slot_name,
+};
+
static struct alchemy_board omsal400_info = {
"Plathome Open Micro Sever AL400/AMD Alchemy Au1550",
omsal400_devices,
@@ -67,6 +85,7 @@
omsal400_pci_intr_map,
omsal400_reboot,
omsal400_poweroff,
+ &omsal400_pcmcia,
};
const struct alchemy_board *
@@ -162,3 +181,67 @@
printf("\n- poweroff -\n");
/* XXX */
}
+
+
+int
+omsal400_slot_irq(int slot, int which)
+{
+ static const int irqmap[1/*slot*/][2/*which*/] = {
+ { 35, 32 }, /* Slot 0: CF connector Type2 */
+ };
+
+ if ((slot >= 1) || (which >= 2))
+ return -1;
+
+ return (irqmap[slot][which]);
+}
+
+bus_addr_t
+omsal400_slot_offset(int slot)
+{
+
+ switch (slot) {
+ case 0:
+ return (0); /* offset 0 */
+ }
+ return (bus_addr_t)-1;
+}
+
+void
+omsal400_slot_enable(int slot)
+{
+
+ /* nothing todo */
+}
+
+void
+omsal400_slot_disable(int slot)
+{
+
+ /* nothing todo */
+}
+
+int
+omsal400_slot_status(int slot)
+{
+ uint16_t inserted = 0;
+
+ switch (slot) {
+ case 0:
+ inserted = !AUGPIO_READ(5); /* pin 5 */
+ break;
+ }
+
+ return (inserted);
+}
+
+const char *
+omsal400_slot_name(int slot)
+{
+ switch (slot) {
+ case 0:
+ return "CF connector Type2 on Static BUS#3";
+ default:
+ return "???";
+ }
+}
Index: conf/OMSAL400
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/conf/OMSAL400,v
retrieving revision 1.2
diff -u -r1.2 OMSAL400
--- conf/OMSAL400 27 Feb 2006 20:50:48 -0000 1.2
+++ conf/OMSAL400 24 Mar 2006 17:45:43 -0000
@@ -19,6 +19,9 @@
aupci* at aubus? addr ?
pci* at aupci?
+aupcmcia* at aubus? addr ?
+pcmcia* at aupcmcia?
+
# Note that this is just fairly random selection of PCI devices.
# Only the hptide controller is actually on-board.
@@ -34,3 +37,11 @@
# USB
usb* at ohci?
usb* at ehci?
+
+# PCMCIA IDE controllers
+wdc* at pcmcia? function ?
+
+# ATA (IDE) bus support
+atabus* at ata?
+
+wd* at atabus? drive ? flags 0x0000