Re: evbmips and MIPS3 timecounters committed

Take a look at the centralization I've done:

__HAVE_GENERIC_TODR in kern/kern_todr.c

and the centralized MIPS CP0 counter clock logic in

sys/arch/mips/mips/mips3_clock.c

In theory, MIPS3 ports could easily lift this and save themselves a lot
of effort/MD specific code.  I'd actually encourage ports that are not
using the MIPS3 clock interrupt to consider switching to it.  I can't
imagine why you not want to use the CP0 counter for clock interrupts
when it is already there.  (Unless maybe you're using CP0 COUNT for some
other purpose?)

    -- Garrett

Simon Burge wrote:
> Garrett D'Amore wrote:
>   
>> Frank Kardel wrote:
>>     
>>> Garrett D'Amore wrote:
>>>
>>>       
>>>> I'm CC'ing the evbmips crowd on this, and the port-mips crowd, because
>>>> they might want to borrow the logic.  It is pretty much the same way on
>>>> any MIPS3 class cpu.
>>>>
>>>>         
>>> Would it be possible to refactor the part for all mips 3 based ports?
>>>       
>> Yes.  There isn't much there actually.  I even considered doing this in
>> arch/mips/, but right now the mips ports do their clock setup each
>> separately.  So it takes some effort (not much) to do that.
>>     
>
> I think we can put the core of the TC implementation in arch/mips, and
> then leave the rest in the per-port clock setup.  It's only a small
> chunk of code, but I think it's better to have a small .c file in
> arch/mips than exactly the same chunk of code duplicated over all MIPS
> ports that have MIPS3 or greater CPUs.
>
> I also think we might be better of using "mips_cp0_count" or similar for
> the timercounter name.  We're using only part of the CP0 register space.
>
> Simon.
>   


-- 
Garrett D'Amore, Principal Software Engineer
Tadpole Computer / Computing Technologies Division,
General Dynamics C4 Systems
http://www.tadpolecomputer.com/
Phone: 951 325-2134  Fax: 951 325-2191